Saturday, 2023-05-20

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Hammdistok I have enabled "bist" and got the read speed 461 MiB/sec, which seems pretty decent01:26
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Hammdistare native ports pipelined? in general, is there any documentation on how to interact with a native port (apart from reading the python code)?01:48
HammdistI see by default I get a 128-bit bus, but there are separate valid/ready on cmd and on wdata and on rdata ... looks complicated01:53
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bjonnh[m]I'm preparing a class for our local hackerspace on FPGAs and half of it is based on LiteX02:49
bjonnh[m]I'm trying to prepare instructions for windows users, and I can't get the colorlight-i5 board to compile properly (works on Linux): http://paste.alacon.org/4774102:50
tpbTitle: Paste à la con (at paste.alacon.org)02:50
bjonnh[m]a simple example with just the litescope works02:51
Hammdistfound some partial answers to my question here: https://freenode.irclog.whitequark.org/litex/2020-05-1403:07
tpbTitle: #litex on 2020-05-14 — irc logs at whitequark.org (at freenode.irclog.whitequark.org)03:07
bjonnh[m]https://bjonnh.github.io/fpga_class_psone/requirements/windows/index.html03:24
tpbTitle: Windows setup :: PS1 FPGA Class (at bjonnh.github.io)03:24
bjonnh[m]That's what I have for the windows setup03:24
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SpaceCoasterbjonnh[m]: I know it isn’t a good solution but commenting out one or both of the add_period-constraint lines for eth_clocks:rx in platforms/colorlight_i5.py worked for me on a Mac.15:03
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bjonnh[m]thanks. this is weird there would be such a diff between platforms15:18
Hammdistif sent commands on multiple ports, and those commands are largely bulk operations (read/write x, x+1, x+2, ...), does litedram interleave them in a reasonable way when sending them to the dram? by reasonable I mean performance should not drop greatly from interleaving15:33
bjonnh[m]<SpaceCoaster> "bjonnh🥬: I know it isn’t a..." <- did you see any impact on the ethernet performance or behavior?15:37
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bjonnh[m]Curiously this function is not called at all on Linux16:57
bjonnh[m]so I think that's a bug in the argument parsing16:57
bjonnh[m]looks like on linux it doesn't go inside generic_toolchain at all17:01
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bjonnh[m]Also this bug still exists: https://github.com/YosysHQ/oss-cad-suite-build/issues/4217:51
bjonnh[m]Looks like trying a fresh install of OSS-cad and installing Litex in it doesn't work  :(18:05
bjonnh[m](on Linux)18:05
bjonnh[m]It does the install, I see all the modules in the site-packages of OSS-cad, but I get18:06
bjonnh[m]python3 -m litex18:07
bjonnh[m]/home/foo/oss-cad-suite/bin/tabbypy3: No module named litex18:07
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bjonnh[m]That's the instructions I'm trying to make (that used to work a couple of weeks back): https://bjonnh.github.io/fpga_class_psone/requirements/linux/index.html18:18
tpbTitle: Linux setup (recommended) :: PS1 FPGA Class (at bjonnh.github.io)18:18
bjonnh[m]That seem to work on Ubuntu, but not Fedora...18:19
bjonnh[m]Hmm ok false alert that seem to have been some environment pollution18:23
bjonnh[m](I would still appreciate if someones that knows these things could have a look at those instructions and see if they could be improved)18:23
bjonnh[m]I think that oss-cad is using a mixture of my local python and the oss-cad one, that's what fails...18:25
bjonnh[m]http://paste.alacon.org/4774218:28
tpbTitle: Paste à la con (at paste.alacon.org)18:28
bjonnh[m]I think that's where all the issues stem from, litex when installing is using 3.11 (from my local system) despite me telling it to use the oss-cad environment18:29
bjonnh[m]I tried all that on a Ubuntu docker with no python installed and all works well. Except that now I get the same error as I did on windows ( AttributeError: 'NoneType' object has no attribute 'name_override')18:35
bjonnh[m]https://github.com/enjoy-digital/litex/commit/fb0c9e846d72fc4fe99ca329cc84a8d2537d3d8d18:37
bjonnh[m]That's the commit that likely broke all that18:37
bjonnh[m]https://github.com/enjoy-digital/litex/issues/169618:42
bjonnh[m]SpaceCoaster: ^^ just going back to before those changes solves the issue18:46
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SpaceCoasterbjonnh[m]: good one!20:10
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