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| amstan | that's it, i made my own pyverilator! I called it pyrilator, lol | 01:35 |
|---|---|---|
| amstan | it looks at the h file verilator produces for a module, finds the ports, creates a cpp file with extern c containing setters and getters for all the ports, and also a way to run eval() | 01:36 |
| amstan | then it uses python's cffi to call it | 01:36 |
| amstan | now i can do instance = pyrilate("mymodule.sv")(); instance.clk=1; instance.eval() | 01:37 |
| amstan | let me know if i wasted my couple of hours and there was a better option, the commit message and doc is pretty detailed: https://github.com/amstan/qoa-fpga/commit/07f7168740c8c6443202296f175ff2b31a26dbe8 | 03:14 |
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| Hammdist | so I'm trying litedram for the first time. I got a successful boot on versa-5g board. however, the memory speed is unimpressive at 21.2MiB/s read and 29.2MiB/s write. is memspeed showing the maximum throughput of the controller or is it doing software writes or what? | 15:39 |
| tnt | The thing displayed at boot is just software soft-core doing read/write in a loop ... | 15:40 |
| Hammdist | here is a paste of the bios boot screen https://paste.ee/p/OTlF7 | 15:40 |
| tpb | Title: Paste.ee - View paste OTlF7 (at paste.ee) | 15:40 |
| Hammdist | so it should be possible to get better performance using a native port, with pipeline perhaps? | 15:41 |
| tnt | yes. | 15:41 |
| tnt | You can actaully enable the built in memory test in the controller and then the bios should have commands to execute a "hw level" benchmark IIRC. | 15:42 |
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