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| _florent_ | MoeIcenowy: sure, if LiteDRAM refresher is failing on some cases, we should fix it yes | 07:23 |
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| _florent_ | MoeIcenowy: If you can open an issue with what you observed, I'll look at it | 07:26 |
| _florent_ | somlo: I'm in vacation this week, but will try to help you with RGMII/SATA on the STVL7325 when I'll be back | 07:26 |
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| MoeIcenowy | _florent_: well I am not sure | 11:39 |
| MoeIcenowy | because it's just the DRAM used is not the same with the DRAM specified | 11:39 |
| MoeIcenowy | which could easily happen in SODIMM cases | 11:39 |
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| joseng | litex | 13:06 |
| joseng | ups :D | 13:06 |
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| _florent_ | MoeIcenowy: Ah OK I see. Antmicro has been working on this, this will probably be integrated in the near future. This changes some timings parameters from static (determined at build time) to dynamic to allow reconfiguring them after reading the SPD EEPROM. | 17:12 |
| cr1901 | Does this mean no need to specify the DRAM IC you have anymore? | 19:25 |
| cr1901 | Or "specify a vendor and a 'similar' DRAM, and litedram will read the EEPROM and attempt to accommodate slightly different DRAMs"? | 19:26 |
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| _florent_ | cr1901: This will be an option since will also use more logic resources. Ex for an FPGA board with soldered DRAMs, it does not make sense to enable it. But for boards with DIMM connectors, it can make sense if you are going to changes mounted DRAMs DIMMs. | 20:43 |
| cr1901 | ahhh true | 20:57 |
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