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| slagernate | finally got litex working on my crosslink-nx board -.- https://github.com/enjoy-digital/litex/issues/1441 | 02:03 |
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| slagernate | albeit the BIOS crc is incorrect... | 03:09 |
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| jeremyh_ | hi everyone | 06:48 |
| jeremyh_ | I'm a bit litex noob trying to play around with my first litex design | 06:48 |
| jeremyh_ | I'm trying to build https://github.com/joshajohnson/ecp5-mini-projects/tree/master/litex/soc-hr | 06:49 |
| jeremyh_ | (it's for the ECP5-mini using nextpnr) | 06:49 |
| jeremyh_ | Unfortunately, I get the following error right near the end of building it | 06:49 |
| jeremyh_ | Info: IOLOGIC component OFS1P3BX_1 connected to PIO Bel X38/Y0/PIOB | 06:49 |
| jeremyh_ | Info: IOLOGIC component OFS1P3BX connected to PIO Bel X35/Y0/PIOAERROR: CE signal or polarity mismatch for IO flipflop IFS1P3BX_1 with other IOFFs at location. | 06:49 |
| jeremyh_ | ERROR: Packing design failed. | 06:49 |
| jeremyh_ | oop | 06:50 |
| jeremyh_ | sorry that should be 4 lines | 06:50 |
| jeremyh_ | im not exactly sure what can cause this problem, if it is an issue with nextpnr or an issue with the code (I'm guessing the latter) | 06:51 |
| jeremyh_ | could anyone please point me in the right direction with how to debug something like this? I'm a bit stuck unfortunately | 06:51 |
| slagernate | may want to check design is small enough (logic/FF and pin count utilization), and that your litex script is targeting the actual device you want (ECP5-Mini, `python3 project/ecp5_mini.py --build --load`, I assume you are using)? | 06:56 |
| jeremyh_ | yep, I am using that command minus the --load | 06:56 |
| slagernate | also, I have better luck running litex on a virtual environment (I used multipass): https://github.com/enjoy-digital/litex/issues/1441 | 06:56 |
| jeremyh_ | LUT4s are at 25% so i don think that is the issue | 06:57 |
| slagernate | may want to post your full script and output on github somewhere. I'm quite new to litex myself, fyi | 06:57 |
| slagernate | is yours a "non 12F" ECP5? The README mentions using `--device=25F` if so | 06:59 |
| jeremyh_ | yeah, the device is a 12F | 06:59 |
| jeremyh_ | i am just using the script as-is from the repo, though I added a single line to fix a build problem with `ident_version` | 07:00 |
| jeremyh_ | i will try to capture a log | 07:00 |
| slagernate | I had a pretty great experience using multipass as VM (not virtual environment). | 07:01 |
| jeremyh_ | i'm currently running it without a virtualenv | 07:05 |
| jeremyh_ | it's a brand new VM ubuntu image with basically not much else installed | 07:05 |
| jeremyh_ | i captured the log here: https://gist.github.com/jeremyherbert/f7c48fdcc349fd5a903665a96a9291f0 | 07:05 |
| jeremyh_ | i have not really used multipass before, so I'm trying to do as little as possible at first while i get something working ;) | 07:06 |
| slagernate | I think multipass isn't required if you have a fresh ubuntu install | 07:09 |
| slagernate | looking at stderr it seems the pin configuration is causing the packing error | 07:09 |
| jeremyh_ | yep, I'm still trying to work out where the packing problem is though | 07:10 |
| jeremyh_ | like which pins are the ones in the design that are causing the conflict | 07:10 |
| slagernate | hm, weird. Not sure what's going on. I guess worst case could possibly start from scratch and create your own board file, assuming there are no other existing examples for that board. | 07:17 |
| slagernate | sorry I can't help much | 07:17 |
| jeremyh_ | no worries, thank you for the help anyway | 07:18 |
| jeremyh_ | I appreciate it | 07:18 |
| jeremyh_ | well, if I remove the valentyusb core from here: https://github.com/litex-hub/valentyusb it builds ok | 07:20 |
| jeremyh_ | so i guess it is a problem with the usb core | 07:20 |
| jeremyh_ | yep, indeed it seems that if I replace the usb-acm uart with a regular uart, the core builds and runs correctly | 07:52 |
| jeremyh_ | so i guess the cdc-acm doesn't support the ECP5-12F ? I see a bunch of references to these IO buffers in the commit logs of the valentyusb litex repo | 07:53 |
| tnt | jeremyh_: seems like it's requesting something that's not possible for the IOBlocks. | 08:17 |
| tnt | Shouldn't be 12F specific, but it could be the exact pins on which USB is. Not all IO blocks are the same. | 08:18 |
| tnt | Could also be some recent change in either nextpnr (like it become more restrictive, or better at checking things) or the core... | 08:18 |
| gatecat | Yeah, it's got better at checking conflicts in the IO flipflops that would result in a silent miscompile, or, because of the bug, even memory corruption | 08:19 |
| gatecat | Quite possibly for USB 1.1 you could get away without them and just use regular flipflops. That may well be what Diamond actually does here anyway (nextpnr errors out where ECP5 IO FFs can't be used, Diamond usually just converts them back to regular ones...) | 08:21 |
| gatecat | For the ECP5 as far as IO flipflops are concerned there should be no differences between IO pins afaik | 08:21 |
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| jeremyh_ | thanks for the tips - yes, I suspected that might be the case about error checking | 09:14 |
| jeremyh_ | i will see what I can do about playing around with the output flipflops | 09:14 |
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| jeremyh_ | Thank you again! I reverted this commit https://github.com/litex-hub/valentyusb/commit/61fb144550e513be0717d3f5910a19a0cc1a6fe9 and now it works! | 09:50 |
| jeremyh_ | I'm not sure where to report this bug though, because the repo is a fork | 09:50 |
| gatecat | actually that pattern looks like it should be okay | 09:51 |
| gatecat | can you zip up the gateware build folder so I can look at this some time? | 09:51 |
| jeremyh_ | sure | 09:51 |
| jeremyh_ | should i create an issue on nextpnr and upload it there ? | 09:55 |
| gatecat | yeah, sounds good | 09:56 |
| jeremyh_ | done: https://github.com/YosysHQ/nextpnr/issues/1095 | 10:00 |
| jeremyh_ | thanks again | 10:00 |
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