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| hammdist | how would I determine whether a particular board is supported with a FOSS toolchain? | 02:51 |
|---|---|---|
| sensille | hammdist: safest bet is still lattice ECP5 or iCE40 fpga. the board itself is of lesser importance | 06:05 |
| sensille | to my knowledge everything else is more or less experimental | 06:06 |
| sensille | but for the smaller fpgas most vendor toolchains are also free and run on linux. but compared to yosys they are a pain to handle | 06:08 |
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| MoeIcenowy | yes, just choose a board with ECP5/iCE40 | 07:02 |
| MoeIcenowy | for iCE40, iCE40UL and iCE5LP is blacklisted | 07:02 |
| MoeIcenowy | for ECP5 I am not sure (my only ECP5 board is just Colorlight "LED screen controller" | 07:03 |
| MoeIcenowy | by the way the iCE40 vendor toolchain is very weird | 07:03 |
| MoeIcenowy | maybe worse than open source one | 07:03 |
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| beltzer | isr.c was moved from the bios directory to libbase (884ee45c289e1a1650937355c6356b3f64ee0c3a). Does this not make it harder to add your own interrupt handlers without modifying libbase for your project? Before you could just specify your own isr function, doing that now throws a linker error. | 11:04 |
| somlo | hammdist: it shows as "out of stock" at the moment, but I'd recommend trying to find out if/when they're going to do another production run of this board: https://shop.lambdaconcept.com/home/46-2-ecpix-5.html#/2-ecpix_5_fpga-ecpix_5_85f | 13:21 |
| tpb | Title: ECPIX-5 (at shop.lambdaconcept.com) | 13:21 |
| somlo | (it can run Fedora-riscv64 on bitstream built with yosys/trellis/nextpnr, so IMHO it's the optimal FOSS-all-the-way-down board out there) | 13:23 |
| MoeIcenowy | somlo: a full rocket? | 14:10 |
| MoeIcenowy | (with this price I can buy a xc7k325t board by QMtech, | 14:12 |
| MoeIcenowy | and +50 euros I can buy a STLV7325 | 14:12 |
| MoeIcenowy | for STLV7325, considering it has a SODIMM slot, it might be able to self-reproduce the gateware someday (but not today, >32bit bus support in LiteX does not exist now | 14:13 |
| MoeIcenowy | and 7-series open source toolchain is also not really usable now | 14:15 |
| somlo | MoeIcenowy: yeah, a single-core "full" double-wide (128-bit memory bus -- 512MB DRAM) Rocket, with sdcard and ethernet | 14:36 |
| geertu | somlo: Care to try https://lore.kernel.org/all/4d07ad990740a5f1e426ce4566fb514f60ec9bdd.1670509558.git.geert+renesas@glider.be on Rocket? | 15:38 |
| tpb | Title: [PATCH] lib: Add Dhrystone benchmark test - Geert Uytterhoeven (at lore.kernel.org) | 15:38 |
| geertu | On orangecrab/vexriscv @ 64 MHz, I got 22 DMIPS (0.3 DMIPS/MHz) | 15:39 |
| geertu | which is far from the claimed 1.44 or 1.57 on https://github.com/SpinalHDL/VexRiscv | 15:40 |
| tnt | geertu: vex is so configurable that it heavily depends on your config. Also highly dependent on your memory system. You'd only reach that with on-chip zero latency memory probably. | 15:55 |
| tnt | Also, those numbers would be running benchmark baremetal with no os overhead. | 15:56 |
| geertu | tnt: So far, Andestech AX45 (in RZ/Five) is the RISC-V core with the highest DMIPS/MHz I have (2.2) | 15:58 |
| tnt | But what fmax do you get with it on the same fpga vs Vex ? :D | 16:00 |
| geertu | tnt: ;-) | 16:02 |
| somlo | geertu: on a nexys-video with 4 Rocket cores (the "full", a.k.a. FPU-enabled variant), I did `echo y > /sys/module/test_dhry/parameters/run` (i.e., without any additional preparation, paramter settings, etc.) | 16:09 |
| somlo | got "CPU3: Dhrystones per Second: 106384 (60 DMIPS)" | 16:10 |
| somlo | I should also mention the cpu clock is 50MHz | 16:11 |
| somlo | I assume only one core is used by default? (in which case I'd expect similar results on any 50MHz "full" Rocket/LiteX system, regardless of core count) | 16:13 |
| geertu | somlo: Thx! 1.2 DMIPS/MHz is not that bad, given that I get 1.5 on U54 and 1.8 on U74 hardcores | 16:13 |
| geertu | somlo: Yes, it's per core | 16:14 |
| somlo | geertu: is this on its way to official upstream? Once it lands, I should add it to the rocket/litex defconfig in `litex-hub/litex-rebase` :) | 16:15 |
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| geertu | somlo: That's the plan. But it's really only intended for testing. | 16:15 |
| somlo | well, yeah, just like the `litex-rebase` branch itself | 16:15 |
| MoeIcenowy | somlo: BTW I did some conditionally-compiled DT at https://github.com/Icenowy/linux-on-litex-openc906 | 16:16 |
| MoeIcenowy | although initially created for OpenC906, I also use this to run on Rocket now too | 16:16 |
| somlo | MoeIcenowy: interesting! Although, long-term, I'd like to take advantage of the `pythondata_cpu_rocket/verilog/generated-src/*.dts` files that are generated by Chisel along with the verilog for each specific variant | 16:23 |
| somlo | which should come in handy if we ever manage to get rid of variants and elaborate the verilog from chisel on-demand | 16:24 |
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| jevinskie[m] | <MoeIcenowy> "for STLV7325, considering it has..." <- Yes rebuilding itself from its bootstraps is an interesting prospect :) | 16:48 |
| jevinskie[m] | It looks like dynamic timing (e.g. delays) support has been upstreamed from antmicro’s verilator fork to the main repo. I should be able to run litex_sim with Micron DDR3 models now :) | 16:51 |
| somlo | yeah, short-term an ECP5 board with a SODIMM slot would be nice :) Medium-term, full yosys/nextpnr support for xilinx 7-series chips (artix/kintex/virtex) would be even more awesome | 17:02 |
| geertu | Any open toolchain for mpfs? | 17:22 |
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