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| MoeIcenowy | _florent_: what should I do when renaming a board? | 02:01 |
|---|---|---|
| MoeIcenowy | e.g. should I try to keep the old name's compatibility? | 02:01 |
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| cr1901 | My own experience is that boards get renamed w/o regard for backwards compatibility | 02:12 |
| cr1901 | this is what happened when most (all?) boards were renamed to have a vendor prefix | 02:12 |
| * cr1901 wonders if this changed | 02:12 | |
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| cr1901 | _florent_: litex_read_verilog doesn't seem to parse "output reg" in the ports list an ignores it. I'm deeply distracted right now, so I can't file an issue. But this at least will remind me hopefully | 04:51 |
| mewt | Oh that reminds me, I guess I should try and gather info for the csr_data_width problem and file a proper issue there too | 04:52 |
| mewt | I'll get on that in a few | 04:52 |
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| _florent_ | MoeIcenowy: we can just rename the boards yes, no need to keep old name's compatibility | 08:25 |
| MoeIcenowy | _florent_: the AXI upconverter of LiteX seems to be broken | 08:38 |
| MoeIcenowy | I tried to create an openC906 SoC with 32-bit width bus (openC906 native width is 64) | 08:38 |
| MoeIcenowy | and it fails with `AttributeError: 'Record' object has no attribute 'dest'` | 08:38 |
| MoeIcenowy | oh sorry it's a down converter in LiteX's name | 08:38 |
| MoeIcenowy | oops I wrongly named it because I forget CPU is master | 08:39 |
| MoeIcenowy | okay it seems to be similar with c24bbedb68ee72d81159ff064c3a64ffe596429a | 09:21 |
| MoeIcenowy | oops that upconverter seems to be just not working at all even with this build fix | 09:51 |
| lolock | Hello, I need a DFI compatible SDRAM PHY (without memory controller). Can I use LiteDRAM to generate an isolated PHY? | 10:04 |
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| mewt | Poked a bit more into litespi and I guess I see the issue -- other cores seem not to have widths hardcoded in their layouts (common.py), I guess the way is to have a function that takes something like liteeth's "dw" as a parameter to make the layout | 16:47 |
| mewt | I can try to do this and submit a PR to be cleaned up over the coming days I guess | 16:49 |
| mewt | I will try to match what liteeth does as an example | 16:52 |
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