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| keesj1 | lo | 05:32 |
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| davebee | I'm trying to connect an interrupt from EventManager() / EventSourceProcess(). The pending register gets set correctly, when my irq source is asserted, but it doesn't generate an interrupt on the processor : I've set the ev_enable() register. I've looked at the uart.py as an example, but can't see how the cpu interrupt line is connected. Where should I look for clues? Thanks. | 10:15 |
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| davebee | Well now my interrupt line seems to be connected, but it no longer generates the C header stubs for that EventManager CSR. | 12:18 |
| davebee | Sorted now. I'm mixing Amaranth modules, VHDL and Litex, so adding an EventManager to my imported Amaranth module caused the issues. | 13:51 |
| davebee | Thank Guido for duck typing | 13:57 |
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| leons | florent: do you think we can get this in reasonably quickly? https://github.com/enjoy-digital/litex/pull/1395 | 18:36 |
| leons | Would allow me to avoid shipping a patch for that in nix-litex | 18:36 |
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