Tuesday, 2022-07-05

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jevinskie[m]Oh my… antmicro added dynamic scheduling to verilator so stuff like #delay works. I wonder if it can run the micron ddr3 model or macronix SPI model (a big part of why I wanted to support iverilog/Questa) :3 let’s see!02:00
tpbTitle: Antmicro · Dynamic scheduling in Verilator - milestone towards open source UVM (at antmicro.com)02:01
jevinskie[m]And the latest version uses C++20 coroutines. Be still my heart :’) https://github.com/verilator/verilator/commit/db0e4eb82f3d9a78c5a8fba86bedcdfd9f610cd202:02
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jevinskie[m]Darn, the ddr3 model still needs more massaging before it will work with antimicros verilator fork03:28
trabucayresomlo: for ecpix5 https://github.com/enjoy-digital/litex/pull/1352 may fix issue05:12
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_florent_jevinskie[m]: antmicro did some simulation with micron ddr3 model and verilator, this hasn't been merged but can still be useful: https://github.com/enjoy-digital/litedram/pull/19608:06
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remy_Hi, first of all I would like tot thank you about all the work putted into this wonderful project. But I'm somehow stuck for a month now with a problem of code execution. I built my own riscv toolchain with the Linux-with-Litex with the VexRiscV as a target of my C++ code. As I need to use libraries/peripherals from Linux, I built the linux version of the Toolchain and tried a simple "Hello World" using iostream library. But I get a weird 08:19
remy_output error saying that it has an "unhandled signal 7 code 0x1 at 0x95bca894 in ld-linux-riscv32-ilp32.so.1". Did you ever had this error ? Do you konw if there is any way to solve it ? Thank you08:19
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somlotrabucayre: thanks, PR 1352 did indeed fix the issue14:44
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jevinskie[m]_florent_: thanks! Beautiful, it’s like they read my mind :P I wonder if the antmicro folks ever sleep? https://github.com/antmicro/litedram/tree/5d8199a0dab3f249e9f3f854b0f7f383ab18b2a8/thirdparty/patches/micron20:00
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