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| xobs[m] | You may be right in that there may not be many peripherals for litex in Renode, but I can bang a renode simulated Peripheral together in a few hours, much to the chagrin of bunnie who spends a month trying to get timing closure in verilog. | 01:01 |
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| xobs[m] | I'm not familiar with the framebuffer, though. I feel I should take a look at it if it's broken. | 01:02 |
| swetland | sounds like it's just the register interface being out of date and probably simple to fix | 01:30 |
| swetland | I'm sure if I was familiar with renode it couldn't be more work than qemu. I was already pretty far along with my qemu port so when renode ended up not "just work"ing out of the box I set it aside for the moment | 01:46 |
| xobs[m] | No worries, like I said, I definitely think more implementations is always better. Let me know if you do want to get it working in the future though. | 01:48 |
| swetland | oh I definitely do. just juggling a bunch of projects | 02:38 |
| _florent_ | jevinskie[m]: in fact for we are already using Bitslip in logic (7-Series Bitstlip has weird behavior and it's easier to have Bitslip in logic to share code between the different PHYs) so it will be possible to reuse it on Max10. | 12:58 |
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| subthreshold | Hi _florent_! I was wondering if you could help me understand this:https://github.com/m-labs/migen/blob/master/migen/genlib/roundrobin.py | 22:57 |
| subthreshold | In line 24, the switch list looks like it's constantly being overriden | 22:57 |
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