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| xenador77 | Is there a guide to adding a board to the supported boards list and/or porting litex to an ice40 dev board? | 03:38 |
|---|---|---|
| xenador77 | I'm capable of using google just wanted to know if there was a definitive "official guide" | 03:39 |
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| _florent_ | amstan: The implementation indeed seems very efficient! I may have a good use-case to test it/use it: I have a SDS1104X-E on my desk, that can also be used as a LiteX dev board that I would like to use as an additional screen, but the 100Mbps Ethernet link is a bit limitating, encoding in QOI on the Host and decoding it in the FPGA could be be enough to have something usable. | 07:42 |
| _florent_ | amstan: It's perfectly possible to integrate verilog in LiteX BTW, we are mostly using it for integrating CPUs in the "open-source" part, but it's heavily used to re-integrate other regular Verilog/System-Verilog/VHDL cores in proprietary projects. | 07:43 |
| _florent_ | subthreshold: The controller integration is probably done by add_sdram in your design, the code is here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L1344-L1519 | 07:45 |
| _florent_ | subthreshold: you add the PHY in your target file (since specific) and add_sdram adds the LiteDRAM core + connections to the SoC. | 07:46 |
| _florent_ | xenador77: Sorry no, we don't have an official guide. I would recommend starting simple: To get a first version of your SoC running, you just need an input clock and a UART | 07:48 |
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| _florent_ | xenador77: So you can just create a platform file with this. You should then be able to build the simple target on it: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/simple.py | 07:49 |
| _florent_ | xenador77: ex when building it for Digilent Arty board: python3 -m litex_boards.targets.simple litex_boards.platforms.digilent_arty --build | 07:49 |
| _florent_ | xenador77: Once it's working, you can then progressively add the specific clocking, peripherals, etc... and create a specific target file for your board | 07:50 |
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| subthreshold | _florent_ thanks so much! That makes sense - for a while i had ignored add_SDRAM as I thought that was adding the memory device model itself. '=( | 07:53 |
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| davebee | I'm trying to get jtagbone working on litex. I have a vexriscv, on an ECP5 (colorlight i9). Is there anything I need to do other than call soc.add_jtagbone()? Perhaps some clock domain I'm not connecting / providing? Can I bring out the JTAG to io pins, rather than connecting to the internal ECP5 JTAGG? | 08:13 |
| davebee | The colorlight i9 extension board has an stm32 device which implements JTAG over USB, 'cmsisdap'. I'm using openFPGALoader. | 08:16 |
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| _florent_ | davebee: Just adding soc.add_jtagbone should be enough yes | 08:30 |
| _florent_ | davebee: then used a .cfg file similar to this: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/prog/openocd_butterstick.cfg | 08:30 |
| _florent_ | davebee: when generating your design, add --csr-csv=csr.csv | 08:30 |
| _florent_ | davebee: then start litex_server: litex_server --jtag --jtag-config=openocd_butterstick.cfg | 08:31 |
| davebee | I have the csv file. I wonder what I'm doing wrong then. I don't have direct access to the JTAG pins. They connect via pogo pins to the STM32. | 08:31 |
| _florent_ | davebee: then you can try to do a litex_cli --regs that should dump the SoC's registers | 08:31 |
| davebee | ltiex-server is looking for vid 0403, pid 6014 | 08:31 |
| davebee | Is there an easy way to bring out the JTAG to io pins? | 08:32 |
| _florent_ | here it's using a FT232 chip, you'll have to adapt this to your programmer | 08:32 |
| _florent_ | not really for this, some HDL parts will be missing, at least for JTAGBone | 08:33 |
| _florent_ | if that's GDB for VexRiscv that you want, it shoud be possible to expose the JTAG pins directly | 08:33 |
| davebee | I think I'll try that then. Thanks. | 08:33 |
| _florent_ | at least for NaxRiscv, Dolu added it recently: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/naxriscv/core.py#L323-L328 | 08:34 |
| davebee | great, I'll take a look | 08:42 |
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| xenador77 | Thanks _florent_ | 09:49 |
| xenador77 | hopefully Upduino-3.1 will be on the list (: | 09:49 |
| xenador77 | will be on the list soon* | 09:50 |
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| davebee | First problem solved : I hadn't set the cpu-variant to "standard+debug". No I have a debug plugin I can see the JTAGG being used and see timing cacls for the jtag interface. But I still can't see the risc-v in a jtag scan. | 10:09 |
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