Sunday, 2022-04-24

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shorneyeah, all of the formal checks are not passing still!, but enough are passing that all actual software tests are passing now02:10
amstanalright, time for me to dive into litex with a toy project:
tpw_rulesamstan: is this your format? is the encoder purely run-length type?03:28
amstantpw_rules: it's not my project, something i found on hacker news a few weeks ago:
tpbTitle: QOI — The Quite OK Image Format (at
amstanit sounds ideal for an fpga03:28
amstani already implemented it in verilog and have shimmed (with verilator) the meaty parts in the converter tools the reference came with03:29
amstantpw_rules: there's a 1 page pdf there for the specification. there's multiple types of "instructions", one is just the literal color, the other is run length, one that does some hashing of a set of previously seen colors, some instructions that do the difference from the previous pixel03:34
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_florent_amstan: nice! I've been very curious about QOI when it came out, also curious to see how simple it can be in an FPGA. If so, this could be really interesting. Happy to play with you with it if you want to integrate your verilog implementation in a LiteX design.09:29
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amstan_florent_: hello! The verilog implementation was pretty simple:
amstani'm still learning about litex (for example I didn't realize it's common to use verilog with it, instead of all python), so i might be saying weird things16:27
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subthreshold_florent_ just wanted to ask a quick question - how do we actually instantiate an lpddr4 mem controller20:40
subthresholdit's less clear to me after looking trhough the build option how that's done20:41
subthresholdAlso thanks for the help on the last question! Forgot to reply earlier...20:44
subthresholdFor example, if we look at sim soc, I can see instantiations of memory model, lpddr4 phy model. However, the controller seems to be absent!20:48
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