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| cr1901 | _florent_: Unfortunately, I don't have an example to show you b/c I absentmindedly cleared my scrollback, but... | 02:24 |
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| cr1901 | What is the point of litex_setup_auto_update(), if git is likely to fail with "you have unstaged changes" when --updating the litex git repo? | 02:26 |
| cr1901 | Ahhh here we go, I had a second repo to duplicate on Linux: http://gopher.wdj-consulting.com:70/paste/2af13b9e-891c-49f7-9739-49812c701c08.txt | 02:28 |
| shorne | somlo: great!, I was just checking too: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mmc/host/litex_mmc.c | 02:53 |
| tpb | Title: litex_mmc.c « host « mmc « drivers - kernel/git/torvalds/linux.git - Linux kernel source tree (at git.kernel.org) | 02:53 |
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| _florent_ | _franck_: To create the standalone modules we first need to determine the interfaces of each module (IO ports and direction) and this has to be done at the top level since there are no clear interface delimitation in Migen. That's probably main thing to add, with it it will be possible to generate the verilog in a single file but with hierarchy (as done by SpinalHDL for example) or in separate files and integrate them with | 07:46 |
| _florent_ | instances. Both cases could be useful. | 07:46 |
| _florent_ | somlo: That's really great! Thanks for the hard work on this. With the work of everyone it's now becoming relatively easy to setup custom Linux systems. | 07:48 |
| _florent_ | BTW, the Radiona team managed to get Linux working on the new ULX4M without too much difficulties: https://twitter.com/RadionaOrg/status/1506715671022952454 | 07:49 |
| _florent_ | somlo: with the LiteSDCard driver used here to copy a raw picture from the SDCard to the framebuffer | 07:50 |
| _florent_ | tnt: We are not reaching the max rated MT/s for DDR4, IIRC I've been using it at max 1600MT/s on deployed designs | 07:54 |
| _florent_ | tnt: It should be possible to revisit the code and get rid of this pulse width violation but this has not been done and hasn't been planned yet | 07:55 |
| tnt | _florent_: I'm just curious how you're supposed to do it. the pulse width violation is too high freq on a clock net right ? And you're going to need 1 GHz on a clock net to run at 2000 MT/s so ... what am I missing ? | 08:00 |
| _florent_ | tnt: The limitation is the max BUFG frequency (891MHz on a -3 device, 775MHz on a -2 device, 667MHz on a -1 device), so we would need to revisit the PHY and have a closer look at the PHY of the MIG to see how they are doing it. | 08:15 |
| _florent_ | tnt: or have an hybrid mode in this case with LiteDRAM as the controller and the PHY from Xilinx for high MT/s. | 08:16 |
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| _florent_ | tnt: the Ultrascale I/Os have a native mode for this (and this is used by the MIG) but I haven't used this yet: | 08:21 |
| _florent_ | https://www.youtube.com/watch?v=ihk7YbZqCKA | 08:21 |
| tnt | _florent_: oh, ok, I see. | 08:43 |
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| Johnsel | hello everyone, question: does litepcie necessarily depend on vendor IP? I believe so, no? For context: I am messing around with an arduino fpga that has a minipcie header connected through to the fpga, but it's Cyclone 10lp has no PCIe support from Altera/Intel. | 11:14 |
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| Johnsel | oh, I solved it myself. Answer is yes. | 11:24 |
| Johnsel | With that solved, jtag-bone does not have any vendor IP requirements, correct? | 11:25 |
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| tnt | Johnsel: huh, yeah it does. | 11:34 |
| tnt | if you want to go through the normal fpga jtag pins, those are normally not user IO and so need some special primitive to access. | 11:34 |
| Johnsel | oh, I see. cyclone10lp_jtag is indeed intel ip naming convention | 11:46 |
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| cr1901 | amaranth's migen compat layer should already create individual verilog modules | 21:16 |
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