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| _franck_ | SpaceCoaster, when you have a module that uses another module you want to be able to see that "hierarchy" in the generated verilog | 08:08 |
|---|---|---|
| _franck_ | currently, you get a monolithic verilog file | 08:09 |
| _franck_ | _florent_: about the hierarchy, I was thinking Migen could generate standalone verilog modules from Modules in the project and we could instanciate those generated modules with self.specials += Instance | 08:12 |
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| tnt | SDRAM:1048576KiB 32-bit @ -1894MT/s (CL-16 CWL-12) I guess there was one too many timing error :D | 09:16 |
| tnt | mmm nope, can't make it meet timing at sys_clk=300M unfortunately. | 10:04 |
| tnt | 250 MHz (hence 2000 MT/s) works fine though. There is a 'pulse width' violation on the pll_4x though. I | 10:22 |
| tnt | I'm kind of wondering how you're supposed to reach 2400 MT/s (rating for that chip) if you already have a pulse width violation at 1 GHz clock net. | 10:23 |
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| somlo | \o/ -- linux/drivers/mmc/host/litex_mmc.c is finally in the official upstream linus tree! | 18:20 |
| somlo | thanks to everyone who helped get it there! | 18:21 |
| gatecat | nice! :D | 18:56 |
| cr1901 | Wow, that's pretty badass | 19:26 |
| tumbleweed | cool | 19:34 |
| SpaceCoaster | _franck_: thanks, some structure would be great | 20:39 |
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