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| tnt | _florent_: you were using data_width=256 for x8 right ? | 07:56 |
|---|---|---|
| _florent_ | tnt: yes | 07:59 |
| _florent_ | https://www.irccloud.com/pastebin/zNIFvxU2/ | 08:02 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 08:02 |
| _florent_ | the other difference is the machine (I'm testing on a H270M-PLUS motherboard with an I9), but since X4 is working, I would have expected X8 to also work on your machine | 08:05 |
| tnt | Ok, I'll give that a shot with sys_clk at 200M and might try to regenerate the .xci in case I screwed it up the first time around. | 08:05 |
| tnt | _florent_: is the fpga on that board faster than a zu11eg-1 ? At sys_clk 200M, I get min-pulse-width violation for the clk_4x for the DDR4. | 08:39 |
| tnt | (damn, yeah, answering my own question the 1525 board has a -2l speedgrade vs -1 speedgrade of the zu11eg) | 08:57 |
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| acathla | If I have two or more memories (Flash) on the same SPI bus, with a different CS_n signal, how can I map that to the wishbone bus? Is it something LiteSPI can do? | 12:39 |
| acathla | I could self.bus.add_slave to two different regions but to the same bus, but I'm not sure how to know which region is accessed, unless I use static addresses. | 12:46 |
| tnt | acathla: doesn't look like it's supported. | 12:55 |
| acathla | That's what I thought :/ | 12:55 |
| acathla | I try with the static address first | 12:56 |
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