Wednesday, 2022-02-09

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jevinskie[m]_florent_: I seem to have found an issue (or misunderstanding) in the Verilog generation. https://gist.github.com/jevinskie/a896250dab9467d66ad9df0683dbddd0#file-deca_leds-py-L64-L7100:34
jevinskie[m]If I use `request_all`, only user_led7 is wired up right: https://gist.github.com/jevinskie/a896250dab9467d66ad9df0683dbddd0#file-opt-request_all-v-L150200:34
jevinskie[m]If I use `request` in a loop, I get all wires hooked up as expected: https://gist.github.com/jevinskie/a896250dab9467d66ad9df0683dbddd0#file-opt_request_loop-v-L1471-L147800:35
jevinskie[m]Here is the yosys script to optimize the slice builders out and see what the direct wirings are. https://gist.github.com/jevinskie/a896250dab9467d66ad9df0683dbddd0#file-opt-tcl00:37
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_florent_ilia__s: thanks, happy to have you prepare the link test yes.06:28
_florent_ilia__s: on the Acorn, https://github.com/enjoy-digital/liteiclink/blob/master/bench/serdes/sqrl_acorn.py can probably be used06:28
_florent_ilia__s: with just the right transceiver.06:29
_florent_ilia__s: on the ECP5, this can be adapted from https://github.com/enjoy-digital/liteiclink/blob/master/bench/serdes/versa_ecp5.py06:30
_florent_ilia__s: then run https://github.com/enjoy-digital/liteiclink/blob/master/bench/serdes/test_prbs.py on both06:30
_florent_ilia__s: if you have a SFP loopback module or another board with SFP, I would also be interested that you had a look at testing this on the SFP connector. Last time I tried I had prbs errors when testing a loopback and would be interested to know if you reproduce this.06:32
_florent_ilia__s: once we have the SFP loopback working, we'll also be able to test 1Gbps Ethernet on the Acorn with https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/a7_1000basex.py06:33
_florent_jevinskie[m]: I'll have a look. platform.request_all is used on targets for similar purpose, so there is probably something different in your code.06:37
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ilia__s_florent_: ok, will do it08:59
_florent_ilia__s: thanks!11:06
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