| *** tpb <[email protected]> has joined #litex | 00:00 | |
| *** mikek_DE1SOC <mikek_DE1SOC!~mikek@cpe000eb66559e0-cm08a7c0b4bdc4.cpe.net.cable.rogers.com> has joined #litex | 00:23 | |
| *** Degi_ <[email protected]> has joined #litex | 01:35 | |
| *** Degi <[email protected]> has quit IRC (Ping timeout: 268 seconds) | 01:37 | |
| *** Degi_ is now known as Degi | 01:37 | |
| *** nelgau <[email protected]> has quit IRC (Remote host closed the connection) | 02:15 | |
| *** nelgau <nelgau!~nelgau@bras-base-mtrlpq2848w-grc-34-174-89-119-57.dsl.bell.ca> has joined #litex | 02:15 | |
| *** nelgau <nelgau!~nelgau@bras-base-mtrlpq2848w-grc-34-174-89-119-57.dsl.bell.ca> has quit IRC (Remote host closed the connection) | 02:15 | |
| *** nelgau <nelgau!~nelgau@bras-base-mtrlpq2848w-grc-34-174-89-119-57.dsl.bell.ca> has joined #litex | 02:16 | |
| *** mikek_DE1SOC <mikek_DE1SOC!~mikek@cpe000eb66559e0-cm08a7c0b4bdc4.cpe.net.cable.rogers.com> has quit IRC (Remote host closed the connection) | 02:25 | |
| *** curtbrune <curtbrune!~curtbrune@2601:646:9600:6271:2d8:61ff:fe57:83f6> has joined #litex | 05:11 | |
| *** nelgau <nelgau!~nelgau@bras-base-mtrlpq2848w-grc-34-174-89-119-57.dsl.bell.ca> has quit IRC (Remote host closed the connection) | 05:13 | |
| *** nelgau <nelgau!~nelgau@bras-base-mtrlpq2848w-grc-34-174-89-119-57.dsl.bell.ca> has joined #litex | 05:51 | |
| *** nelgau <nelgau!~nelgau@bras-base-mtrlpq2848w-grc-34-174-89-119-57.dsl.bell.ca> has quit IRC (Ping timeout: 256 seconds) | 05:56 | |
| *** nelgau <nelgau!~nelgau@bras-base-mtrlpq2848w-grc-34-174-89-119-57.dsl.bell.ca> has joined #litex | 05:58 | |
| *** nelgau <nelgau!~nelgau@bras-base-mtrlpq2848w-grc-34-174-89-119-57.dsl.bell.ca> has quit IRC (Ping timeout: 256 seconds) | 06:02 | |
| *** nelgau <nelgau!~nelgau@bras-base-mtrlpq2848w-grc-34-174-89-119-57.dsl.bell.ca> has joined #litex | 06:04 | |
| *** nelgau <nelgau!~nelgau@bras-base-mtrlpq2848w-grc-34-174-89-119-57.dsl.bell.ca> has quit IRC (Ping timeout: 240 seconds) | 06:08 | |
| *** Martoni42 <Martoni42!~Martoni@2a03:d604:103:600:2ad2:44ff:fe23:2f72> has joined #litex | 07:14 | |
| *** nelgau <nelgau!~nelgau@bras-base-mtrlpq2848w-grc-34-174-89-119-57.dsl.bell.ca> has joined #litex | 07:50 | |
| *** nelgau <nelgau!~nelgau@bras-base-mtrlpq2848w-grc-34-174-89-119-57.dsl.bell.ca> has quit IRC (Ping timeout: 256 seconds) | 07:55 | |
| *** rlittl01 <[email protected]> has joined #litex | 09:05 | |
| _florent_ | nickoe: The issue seems related to write latency calibration, you can try to disable it by commenting: https://github.com/enjoy-digital/litedram/blob/master/litedram/init.py#L921-L922 | 09:08 |
|---|---|---|
| nickoe | _florent_: Hmm, ok I am not sure if there was a way to change it, but I just modified the default set in class S7DDRPHY(Module, AutoCSR): and rebuilt it, now it do seems to pass with OK. https://dpaste.com/64WCPW3DL.txt | 11:34 |
| nickoe | Is that a "new feature" or is that a clear indication on something I may have misconfigured? | 11:35 |
| nickoe | I set the settings to what is described in https://download.enclustra.com/public_files/FPGA_Modules/Mars_AX3/Mars_AX3_User_Manual_V06.pdf page 25 or section 2.14.4 Parameters | 11:46 |
| nickoe | Now ehn I try to load the demo.bin it does not appear to run. | 11:57 |
| nickoe | but I note this when I build it: warning: memory region `main_ram' not declared full log: https://dpaste.com/CP7JNT8PU.txt | 11:58 |
| nickoe | I should be on the latest commit of litex so this "should" be included https://github.com/enjoy-digital/litex/pull/1007 | 12:00 |
| nickoe | But something must have changed, because the old demo.bin on an sdcard fails the same way. Maybe there are more that I ened to change to run agianst the latest litex. | 12:16 |
| *** joseng <[email protected]> has joined #litex | 13:44 | |
| *** Wolfvak <Wolfvak!~Wolfvak@user/wolfvak> has joined #litex | 14:13 | |
| nickoe | Is there a good way to install the symbiflow toolchain for use with litex+ | 15:45 |
| *** lexano <[email protected]> has quit IRC (Ping timeout: 256 seconds) | 16:54 | |
| *** lexano <[email protected]> has joined #litex | 17:06 | |
| _florent_ | nickoe: The default main_ram has been removed from the simulation, you have to explicitly enable it (with --integrated-main-ram-size or --with-sdram) | 17:38 |
| *** Martoni42 <Martoni42!~Martoni@2a03:d604:103:600:2ad2:44ff:fe23:2f72> has quit IRC (Ping timeout: 240 seconds) | 17:50 | |
| *** forksand <[email protected]> has joined #litex | 19:22 | |
| *** curtbrune <curtbrune!~curtbrune@2601:646:9600:6271:2d8:61ff:fe57:83f6> has quit IRC (Quit: Client closed) | 19:33 | |
| nickoe | Mm, ok, _florent_, but does it explain why it does not run on hardware? | 19:49 |
| nickoe | I do like this when building ./mars_ax3.py --build --integrated-rom-size=0x10000 --with-spi-sdcard --load --csr-csv=csr.csv | 19:49 |
| nickoe | When I add --integrated-main-ram-size 0x10000 I get: AttributeError: 'BaseSoC' object has no attribute 'sdram'. Did you mean: 'sram'? | 19:53 |
| nickoe | i guess I should double check I can run the demo app in lxsim.. | 20:00 |
| *** zjason <[email protected]> has quit IRC (Read error: Connection reset by peer) | 20:01 | |
| *** zjason <[email protected]> has joined #litex | 20:03 | |
| nickoe | How is it that I load the demo.bin in the simultor lxsim? It is not mentioned here, only with lxterm, https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU | 20:19 |
| nickoe | iI can make the lx_server connecto the sim and use litex_cli to get the ident from the simulation, BUT how do l load the demo.bin then? | 20:33 |
| _florent_ | nickoe: https://freenode.irclog.whitequark.org/litex/2021-04-20#29709311 | 20:35 |
| tpb | Title: #litex on 2021-04-20 — irc logs at whitequark.org (at freenode.irclog.whitequark.org) | 20:35 |
| nickoe | _florent_: But it does not run for me, I just get the Liftoff! | 20:36 |
| nickoe | that is "litex_sim --ram-init=demo.bin" | 20:36 |
| nickoe | Just running litex_sim boots the bios just fine. | 20:39 |
| _florent_ | litex_sim --integrated-main-ram-size=0x10000 | 20:40 |
| nickoe | I am on litex commit 321b91d5 (HEAD -> master, origin/master, origin/HEAD) Merge pull request #1134 from fjullien/efinix_titanium_support | 20:40 |
| _florent_ | litex_bare_metal_demo --build-path=build/sim | 20:40 |
| _florent_ | litex_sim --integrated-main-ram-size=0x10000 --ram-init=demo.bin | 20:40 |
| nickoe | The last one do run | 20:41 |
| nickoe | So maybe I need to migrate from --integrated-rom-size=0x10000 to --integrated-main-ram-size=0x10000 in my target? | 20:46 |
| nickoe | _florent_: Is that --ram-init option supposed to support a boot.json? | 20:47 |
| nickoe | For me it appaers that Vsim (verilator) crahes | 20:48 |
| nickoe | %Error: mem_2.init:16384: $readmem file address beyond bounds of array | 20:48 |
| nickoe | Mm, I can't figure out why i errors with thatit not being able to find the sdram attribute ... maybe I should take a walk and get some fresh air | 20:58 |
| nickoe | Has this construct changed? I mean, the location of the sdram object? | 21:07 |
| nickoe | self.sdram.crossbar.get_port(mode="read", data_width=32, reverse=True), | 21:07 |
| _florent_ | except adding the --integrated-main-ram-size, things haven't changed | 21:08 |
| nickoe | This is my code, and as far as I can tell it does not like the self.sdram anymore there | 21:09 |
| nickoe | https://github.com/nickoe/litex-boards/blame/mars_ax3_sim_2021.12.18/litex_boards/targets/mars_ax3.py#L212 | 21:09 |
| nickoe | maybe caused my be not doing theese changes properly?? https://github.com/nickoe/litex-boards/commit/5eecf4f5b49a25bc386e15ed6120863e5efb6f6c | 21:10 |
| nickoe | I can't explain why the self.sdram does not exist, but I can't really explain how it get added in the first place because of the attr magic chcecks, so it is a bit hard to navigate. | 21:16 |
| *** lexano <[email protected]> has quit IRC (Remote host closed the connection) | 21:36 | |
| nickoe | When I don't add the new --integrated-main-ram-size then it builds fine.. so it must be dependent on that. | 21:36 |
| nickoe | well, there is of couser tthe check here.. https://github.com/nickoe/litex-boards/blame/mars_ax3_sim_2021.12.18/litex_boards/targets/mars_ax3.py#L129-L144 but should I just remove that check? | 21:41 |
| *** lexano <[email protected]> has joined #litex | 21:42 | |
| nickoe | hmm, no it appears that sections is called a couple of time. | 21:45 |
| nickoe | When "if not self.integrated_main_ram_size and with_sdram:" is not true, hos is the add_sdram then called for the litex_sim.py? | 22:56 |
| nickoe | I can't figure out how to add a brakpoint on just a function name in pycharm. | 22:56 |
| nickoe | oh, right, I could of course just break in the function | 22:56 |
| nickoe | So it is not called.. _florent_ how is self.sdram then added in the case of "litex_sim --integrated-main-ram-size=0x10000 --ram-init=demo.bin --with-sdram" | 22:57 |
| nickoe | mm, maybe I don't want integrated-main-ram-size at all for my setup? | 23:18 |
| nickoe | Is that some sdram that is insude the fpga for some models or? | 23:19 |
| *** mikek_DE1SOC <mikek_DE1SOC!~mikek@cpe000eb66559e0-cm08a7c0b4bdc4.cpe.net.cable.rogers.com> has joined #litex | 23:32 | |
| mikek_DE1SOC | Florent: tnt: Great news !! I wa able to compile the fairwaves.py script!! Let me know what you wanted for me to do next!!! | 23:55 |
| mikek_DE1SOC | https://pastebin.com/TNXg3k1H | 23:55 |
| tpb | Title: Fairwaves_compile - Pastebin.com (at pastebin.com) | 23:55 |
| *** TMM_ <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.) | 23:55 | |
| *** TMM_ <[email protected]> has joined #litex | 23:55 | |
| mikek_DE1SOC | But just to clarify! I have the OLD XTRX, the first generation first generation of the card. Not sure if the FPGA is xc7a__50__tcpg236-2??? I think mine is the 35. | 23:57 |
| mikek_DE1SOC | unless they only made 1 version... | 23:58 |
| mikek_DE1SOC | yeah the CS is the 35.... | 23:58 |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!