Wednesday, 2021-09-08

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sajattack[m]<Melkhior> "sajattack: the L2 matters..." <- thanks for the tip, got my 8 fpus running now 😄 https://hastebin.com/aqafuhenux.apache04:19
tpbTitle: hastebin (at hastebin.com)04:19
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sajattack[m]anyone know what to do about this buildroot error? https://hastebin.com/oyocegavok.rb04:39
tpbTitle: hastebin (at hastebin.com)04:39
trabucayresajattack[m]: it's a mismatch between linux header (Toolchain -> Custom kernel headers series) and your kernel05:45
sajattack[m]yeah I got it sorted I think by forcing it to 5.12 in buildroot05:45
sajattack[m]even though I'm running 5.1405:45
trabucayreneed to select BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_12 for Toolchain -> Custom kernel headers05:46
sajattack[m]so not sure05:46
trabucayregrep PATCHLEVEL output/build/linux-something/Makefile05:46
trabucayreand 05:46
trabucayregrep PATCHLEVEL output/build/linux-header*/Makefile05:47
trabucayreand if you modify linux header version you must run `make clean` before `make`05:48
sajattack[m]yeah that's what I did I think05:49
sajattack[m]but I used the menuconfig05:49
sajattack[m]* running 5.14 on my host05:50
trabucayrenot your host :)05:50
sajattack[m]ok05:51
trabucayrelinux version must be the same for linux-header (toolchain) and kernel for your target 05:51
sajattack[m]ah ok05:51
sajattack[m]so why wasn't it to start with?05:51
sajattack[m]it was set to like "match whatever"05:52
sajattack[m]and I just overrode it to 5.1205:52
trabucayrewhen linux header is not explictly selected default one is used05:52
sajattack[m]is it because of the buildroot version I downloaded?05:52
sajattack[m]now I'm uploading a 12MB rootfs at 8KB/s05:53
trabucayrefor current master branch it's 5.1305:54
sajattack[m]<_florent_> "BTW once you have something..." <- https://github.com/litex-hub/linux-on-litex-vexriscv/issues/24905:54
trabucayrehttps://git.buildroot.net/buildroot/tree/package/linux-headers/Config.in.host#n905:54
tpbTitle: Config.in.host « linux-headers « package - buildroot - Buildroot: Making Embedded Linux easy (at git.buildroot.net)05:54
sajattack[m]yeah it was set to "same as kernel being built"05:54
sajattack[m]and I was building 5.1205:54
sajattack[m]so I don't really understand why it had to change to 5.1205:55
sajattack[m]but whatever05:56
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sajattack[m]<Melkhior> "depends on your use case I guess..." <- did you recompile on-device? I'm trying to figure out how to get a compiler into the buildroot, seems buildroot doesn't let you do that because they want to save space?07:28
sajattack[m]all it'll give me is binutils07:29
sajattack[m]I guess I could do a filesystem overlay07:29
sajattack[m]but then I'd need a way to cross-compile gcc which doesn't sound like a good time07:30
sajattack[m]I've done it before raspberry pi actually07:32
sajattack[m]but it wasn't especially fun07:32
sajattack[m]I think I just delayed my "what the hell do I do with this now" by a few days 😆07:45
sajattack[m]but no regrets07:45
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cr1901>(3:30:28 AM) sajattack[m]: but then I'd need a way to cross-compile gcc which doesn't sound like a good time11:50
cr1901I wish the targets "all-{,target}-*" were documented instead of me having to read the source of the gcc Makefile (which is maybe the only use I've seen of GNU autogen in the wild)11:50
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_florent_sajattack[m]: Thanks for the issue, I'll try to simplify using this configuration.13:35
_florent_That's also a bit sad to see 8KB/s upload on a PCIe link is usually use on other designs for >12Gbps DMA xfers :) I'll have a closer look at litex_server/litex_term  use over PCIe to see where we loose that much efficiency...13:38
_florent_tpw_rules: Thanks for the files, I just had a look at it: They are very similar to the one I'm generating locally and ./sqrl_acorn.py --with-pcie --uart-name=crossover --build also fails here.13:40
_florent_I'll improve the constraints, for now you can comment these lines: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/sqrl_acorn.py#L107-L11113:41
_florent_tpw_rules: sajattack[m] is using a very similar configuration I think13:42
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_florent_tpw_rules: the build should be fixed with: https://github.com/enjoy-digital/litex/commit/6c2bc0232370c4af13cc66db0847522105f9101314:29
_florent_and https://github.com/litex-hub/litex-boards/commit/129b95f9b514dd469674d22e2304f99e9515c80514:29
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sajattack[m]_florent_: would I see any benefits updating to that or do the timing constraints not effect much?16:09
_florent_not really but the P&R will be faster16:09
sajattack[m]oh ok16:10
sajattack[m]yeah I didn't expect it would change much16:10
sajattack[m]faster pnr is good though16:11
sajattack[m]seeing as I'm building hexacore hexafpu16:11
sajattack[m]looking for things to do and having trouble sleeping last night, I got a rust binary compiled for vexriscv linux using the rust std library16:12
sajattack[m]I'm about to see if it works once the cpio uploads16:12
sajattack[m]96%16:12
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sajattack[m]https://hastebin.com/tefekadegu.typescript16:14
tpbTitle: hastebin (at hastebin.com)16:14
sajattack[m]🥳16:15
_florent_sajattack[m]: nice16:24
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tpw_rulessajattack[m]: can you share how you got that running? i am interested in giving it a whirl on my board; have been having trouble getting it to do much of anything interesting16:47
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sajattack[m]I built this for 32 bit and used it as the linker for the rust target riscv32gc-unknown-linux-gnu with -Zbuild-std https://github.com/riscv-software-src/riscv-gnu-toolchain16:48
tpw_rulesi more mean the gateware and loading linux onto it16:49
sajattack[m]https://gist.github.com/sajattack/701a8d677ec01fe51b423ebbfa013c22 oh ok, I thought you meant the rust16:50
sajattack[m]for the bitstream, I made some notes here https://github.com/litex-hub/linux-on-litex-vexriscv/issues/24916:50
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jevinskie[m]I modified serial2tcp into serial2udp so you get first/last framing. Hooked it up to SPIMaster with a simple stream FSM for a SimSPIMaster :)20:51
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G33KatWorkheyjo! I have a question about simulating something I am currently writing using litex - it might be more of a migen question, but anyway, here we go: I am trying to build a receiver for a protocol. To test the synchronization features of my receiver, I need a sender in a testbench in a different clock domain than the receiver. I already have two generators in my testbench, one for the transmitter which 21:49
G33KatWorkshoves bits with the right timing over a pad into the receiver running in another generator. Now to simulate a slowly drifting clock, I want the sender and receiver generator to run in different clock domains. Let's say the receiver runs at 10MHz, I want the sender to run at a sliiiighly slower or fast clock. Is that possible? I couldn't find an example that actually does this, so I thought I'd ask here.21:49
G33KatWorknevermind. I just got the idea to check out the more complicated external cores like litesata and I immediately found it. Just add clocks in the clocks dict and change the list of generators passed to run_simulation to a dict of lists where the key is the clock domain name and the value the list of generators22:00
G33KatWorklike this: https://github.com/enjoy-digital/litesata/blob/master/test/test_bist.py#L69-L7622:00
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