Friday, 2021-09-03

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pftbestDoes anyone know why it is using RX pad here instead of GTX ? https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/gmii.py#L7209:31
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pftbestsorry, gtx is an output pin10:25
pftbestnow i get it10:25
futarisIRCcloudhttps://www.linkedin.com/posts/xianjun-jiao-7a569641_openwifi-opensource-hardware-activity-6839490827685789696-C0H110:37
tpbTitle: XianJun Jiao on LinkedIn: #openwifi #opensource #hardware (at www.linkedin.com)10:37
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esp88Hi/bonjour! 14:02
esp88(let me know if you prefer the question in english)14:02
esp88Tout d'abord, je commence à découvrir litex et je trouve que c'est un super projet!14:02
esp88J'ai une question par rapport à litesata. J'ai une carte KCU105 et j'essaie d'executer test_bist.py avec un SFP SATA sans succès. 14:03
esp88J'ai essayé de deux façons:14:03
esp88#1:14:03
esp88Ø litex-boards/litex_boards/targets/xilinx_kcu105.py --build --load --with-pcie --with-sata --sys-clk-freq=10000000014:03
esp88Ø litex_server --uart --uart-port=/dev/ttyUSB114:03
esp88Dans le test #1, test_bist.py ne semble pas trouver les configuration sata_bist dans le csr. J'ai vu qu'elles étaient ajoutés dans litesata/bench/kcu105.py, j'ai donc essayé de builder celui-ci dans le test #2. 14:03
esp88#2:14:04
esp88Ø cd litesata/bench14:04
esp88Ø ./kcu105.py --build --load --connector sfp14:04
esp88Ø litex_server --uart --uart-port=/dev/ttyUSB114:04
esp88Dans le test #2, le port uart ne semble pas actif. 14:04
esp88Auriez-vous une piste de solution à me suggérer svp? 14:04
esp88(tldr in english: Great project and I'm trying to test libsata with test_bist.py and a KCU105 but no success yet. Test #1 above does not seem to find "sata_bist" variable in the csr and the uart does not seems active with test #2.  Let me know if you have any suggestions please :) )14:14
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jevinskie[m]_florent_: I want to expose the litescope scope_trig (which I know is a "synthetic" signal) to other modules so I can kick off a FSM when the scope triggers. What signals should I fish out of the Trigger module? enable & hit?16:10
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_florent_esp88: Hi, sorry you already left but if you read the logs, I would recommend test #2. With your steps, you should be able to execute test_bist.py. If you have trouble, try to do a litex_cli --regs to see if you are able to access the registers of the SoC over the bridge17:06
_florent_jevinskie[m]: you can use _Trigger.source.hit 17:08
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esp88I am still here, thanks _florent_ for the answer :) I will try to follow your recommendation. 17:20
esp88Does lxterm is supposed to work when I build ./kcu105.py (i.e: test #2)?17:21
esp88If yes, I will try to troubleshoot that first because it does not on my side...17:22
_florent_esp88: no, this design does not have a CPU, just the SATA core + bist and a bridge to control it from the Host17:22
esp88ok thanks17:23
_florent_I have the hardware for this bench, so if you still have troubles I can set it up and give more help17:27
esp88Perfect, thank you, I appreciate your help17:28
esp88Second try for test #2 from scratch did work :)  Not sure what I have done wrong the first time... Thanks again for your help _florent_!17:44
_florent_great!17:45
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jevinskie[m]_florent_: thanks, it seems to work using just hit instead of enable & hit :)18:23
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pauluzsHi I'm experiencing about a 1 in 20 builds success rate while trying : linsn_rv901t.py --build20:48
pauluzsfor the linsin car, ise 14.7 ubuntu 20.04. tried current machine, vm and a fresh install. 20:49
pauluzsIt mostly starts to hang on Phase 9.8  Global Placement20:49
pauluzsERROR:Place:543 - This design does not fit into the number of slices available20:49
pauluzsAny advise? set the environment variable XIL_PAR_ENABLE_LEGALIZER to 1  doesn't seem to help20:50
DegiIt sounds like the design is too large to fit onto the FPGA, I guess on some compilations it gets jucky and fits just right22:52
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