Friday, 2021-07-02

« Thursday, 2021-07-01 Index Saturday, 2021-07-03 »
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_florent_chiefwigms: I just prepared the Ultrascale+ GTYE4 BaseX PHY: https://github.com/enjoy-digital/liteeth/commit/2f4964cf56fd5258eda21448269924da0821bfca11:03
_florent_and a bench design for it on BCU1525: https://github.com/enjoy-digital/liteeth/commit/c294a3848ecc038f7f8e2e334a4da13f8b1dcf4e11:04
_florent_it compiles fine but does not yet seems to be working. I'm not able to spend more time on it now, but maybe you could try it on your hardware11:05
chiefwigmssure13:36
chiefwigmsi'll compare it with mine - for whatever reason, it kept saying one of the clocks wasn't routed completely13:37
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_florent_chiefwigms: Ah, I also had this issue and connected the refclk to the GTGREFCLK to avoid it: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/usp_1000basex.py#L61113:58
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chiefwigmscompiled for me, but when i load a target (kcu116) w/ ethernet, it only shows lo and sit0 on ifconfig15:28
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OmkarBhilare[m]Where I can find the info about the inputs in the yml file like supported device, sdram module etc15:55
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OmkarBhilare[m]https://github.com/BeagleWire/litedram/blob/a3aa4907f11f654dc2df58e13903ec99fad69b6f/litedram/modules.py#L48416:04
OmkarBhilare[m]okay got the ram which I wanted16:05
OmkarBhilare[m]https://github.com/enjoy-digital/litedram/blob/a3aa4907f11f654dc2df58e13903ec99fad69b6f/litedram/modules.py#L48416:05
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chiefwigmsany idea on how to troubleshoot?16:44
_florent_chiefwigms: I will try to double check the code next week17:09
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chiefwigmsthanks17:17
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