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| _florent_ | Hi chiefwigms, sorry I got your mail but haven't been able to answer yet | 06:28 |
|---|---|---|
| _florent_ | The 1000basex support for Ultrascale+ has indeed not been done yet, but this should not be too complicated: | 06:29 |
| _florent_ | - for 7-series/Ultrascale, the parameters are directly extracted from the generated files of the wizard configured for as SGMII PHY | 06:30 |
| _florent_ | - the parameters are also in the same order than the wizard, so it's easy to integrate them with a diff tool | 06:31 |
| _florent_ | - so supporting GTYE4 instead of GTHE3 should be a matter of remplacing the instance in the ku_1000basex phy | 06:32 |
| _florent_ | I could have a look and provide at least a skeleton if you want | 06:33 |
| _florent_ | In the long term, I would like to rely directly LiteICLink for the 1000basex PHYs (that already has GTYE4 support), but this work hasn't been started yet | 06:34 |
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| chiefwigms | Hey _florent_ - thanks! i'll give that a shot.. i'll let you know in a few hours if that worked.. thanks! | 14:45 |
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| _florent_ | chiefwigms: ok great, in case you don't get it working, I could also help and do some tests on hardware | 15:15 |
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| chiefwigms | so i generated one the eth core for the kcu105 (ku_1000basex.py) | 17:11 |
| chiefwigms | some of the parameter values don't match up (granted i'm using viviado 2021) | 17:12 |
| chiefwigms | but where do the i_ & o_ values come from? | 17:12 |
| chiefwigms | like ` i_TXCTRL0 = Cat(*[tx_data[10*i+8] for i in range(2)]),` | 17:12 |
| chiefwigms | or some of the o_ params just call Open(), but others have internal variables | 17:13 |
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| rom | hi | 18:05 |
| rom | I'm working on building a SoC with Litex, currently running the Linux on Litex demo just fine, and is looking to customize it a bit | 18:05 |
| rom | I'd like to change the DDR IP to an SDRAM controller (to use SDRAM instead of DDR). Can anyone point me in the right direction? | 18:06 |
| rom | Thanks | 18:06 |
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| chiefwigms | i think i see where the values came from... did you do any custom input parameters for the wizard? | 19:50 |
| chiefwigms | i can send a pastebin of diffs for the kcu105 | 19:50 |
| alanvgreen | rom: Typically you'd be working with an existing board from litex-boards. The board definition in the target file will add the correct type of ram for the board. If you have new board kind of board, you could make new platform and target files to match. | 19:59 |
| alanvgreen | rom: If you adding RAM via a PMOD or some other connector, you will probably want to subclass your board's target SoC target. In the constructor, make a PHY and pass it to call add_sdram() - see litex_boards/targets/radiona_ulx3s.py for an example. You'll need to define the signals returned by platform.request("sdram"), either by modifying the corresponding platform file or by calling platform.add_extension() | 20:10 |
| chiefwigms | https://pasteboard.co/K9cBBul.png | 20:10 |
| tpb | Title: Pasteboard - Uploaded Image (at pasteboard.co) | 20:10 |
| chiefwigms | do any of those diffs matter (short of TXCTRL*/TXDATA/TXUSRCLK*/GTHRX*)? | 20:11 |
| chiefwigms | (i meant anything that's a scalar type binary/dec/string) | 20:12 |
| alanvgreen | rom: oh, I see an the terasic_de10nano board optionally add sdram via a connector - that would be a good starting point | 20:13 |
| _florent_ | chiefwigms: your parameters seem really different than the one we have, I'm not sure the same input settings have been used | 21:03 |
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| _florent_ | chiefwigms: I could try to generate the Ultrascale+ settings tomorrow if you want | 21:05 |
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| OmkarBhilare[m] | Hello, Today in my gsoc project I finished gpmc to wishbone wrapper on beaglewire (fpga cape for beaglebone). | 21:08 |
| OmkarBhilare[m] | I wanted to interface SDRAM to the fpga using litedram. | 21:08 |
| OmkarBhilare[m] | Can you please provide me a skeleton/support for the standalone sdram. | 21:08 |
| OmkarBhilare[m] | <_florent_ "For SDRAM, the initialization is"> Once the ip is produced, I believe I can do this on my own. | 21:09 |
| chiefwigms | 🤷♂️ sure | 21:35 |
| chiefwigms | https://pasteboard.co/K9cBBul.png | 21:38 |
| tpb | Title: Pasteboard - Uploaded Image (at pasteboard.co) | 21:38 |
| chiefwigms | sorry.. wrong window | 21:39 |
| chiefwigms | that was just a diff between a generated vivado 2021.1 (kcu105 which is a kintex ultra) and what's in the liteeth repo | 21:39 |
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