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| whitequark[cis] | yeah sorry i misled you for a bit with the pseudocode | 00:04 |
|---|---|---|
| whitequark[cis] | glad it works now | 00:04 |
| whitequark[cis] | re: the NOREG, maybe if you remove init value from that register it will fold it into the BRAM... | 00:05 |
| whitequark[cis] | you could write a yosys script to delete the init attribute from a signal or smth | 00:05 |
| whitequark[cis] | or try editing the verilog first to remove the = 0 | 00:05 |
| ysionneau | I don't see initial with = 0 value for the memory nor for the output reg | 00:08 |
| ysionneau | or maybe that's not what you meant? | 00:08 |
| whitequark[cis] | the register you're adding (self.source.data) | 00:10 |
| whitequark[cis] | that would have an init value in migen | 00:10 |
| whitequark[cis] | smth like reg source_data = 0; probably | 00:11 |
| ysionneau | ah yes indeed | 00:12 |
| ysionneau | reg [15:0] packet_buffer_source_source_payload_data = 16'd0; | 00:12 |
| ysionneau | let's try | 00:12 |
| ysionneau | na, it's still NOREG | 00:13 |
| ysionneau | maybe yosys never generates outreg by itself? | 00:14 |
| ysionneau | https://paste.centos.org/view/79d71fcb | 00:15 |
| tpb | Title: Untitled - Pastebin Service (at paste.centos.org) | 00:15 |
| ysionneau | seems so, IIUC | 00:16 |
| whitequark[cis] | it would be the memory_libmap pass that does it, if it's implemented | 00:16 |
| ysionneau | I would have to do self.specials += Instance() but ... I would lose the portability of the code | 00:16 |
| whitequark[cis] | no idea if it is | 00:16 |
| whitequark[cis] | yeah | 00:16 |
| ysionneau | from a quick look it seems all is hardcoded to NOREG | 00:18 |
| ysionneau | it's being late for me here, thanks again for your precious help! | 00:19 |
| ysionneau | gn8! | 00:19 |
| whitequark[cis] | nite! | 00:23 |
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