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| Adrien[m] | Hi ! I've recently proposed a contribution to optimize mux mapping for xilinx 7-series techno : https://github.com/YosysHQ/yosys/pull/5202 | 06:53 |
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| Adrien[m] | I would like to enable equivalence check for all testcases, but I would need to specify the range of values of interest for the mux selection input. Can anyone advise how to do that ? | 06:53 |
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| Hammdist | techmap not working as expected https://paste.ee/p/hxAGbIor can anyone give any pointers? a lut of width 1 that appears to be performing a NOT function is not being replaced | 23:24 |
| tpb | Title: Paste.ee - View paste hxAGbIor (at paste.ee) | 23:24 |
| Hammdist | assign _0108_ = 2'h1 >> _0134_[0]; <--- this is what it looks like in write_verilog | 23:25 |
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