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| mkudinov | Hey guys, been trying to locate this issue with Yosys on my DVI design for a while now. What additional info I discovered other than my DVI doesn't work after certain Yosys commit (23b3638c1e9a67c49e7e5f1208250c3e786da47a): my top module and diff signal module has the same clock port name (clk_i), if I rename the clock port on either on these | 10:27 |
|---|---|---|
| mkudinov | modules, the issue goes away. Also, if I synthesize diff signal module separately, write it as RTLIL, then read its RTLIL with the rest of design and synthesize again, the issue goes away | 10:27 |
| mkudinov | How can I proceed further? Design is quite large, diffs are huge. If I try to make it smaller (by partial synth), the issue goes away | 10:28 |
| mkudinov | Also, passing -noalumacc to synth pass doesn't fix the issue | 10:28 |
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