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| Adrien[m] | vancz: yes, I've implemented my own operators netlist-level for Xilinx 7-series FPGAs, for specific purposes, mainly low quantization | 10:06 |
|---|---|---|
| Adrien[m] | https://gricad-gitlab.univ-grenoble-alpes.fr/prostboa/hwopt-xilinx-7series | 10:06 |
| tpb | Title: Adrien Prost-Boucle / hwopt-xilinx-7series · GitLab (at gricad-gitlab.univ-grenoble-alpes.fr) | 10:06 |
| Adrien[m] | Example with a 7-input ternary adder block, wth direct instantiation of LUTs and CARRY, the synthesis tools do recognize the primitives and don't touch these implems, that is convenient. | 10:08 |
| Adrien[m] | https://gricad-gitlab.univ-grenoble-alpes.fr/prostboa/hwopt-xilinx-7series/-/blob/main/hdl/adder_7in_ter.vhd?ref_type=heads | 10:08 |
| tpb | Title: hdl/adder_7in_ter.vhd · main · Adrien Prost-Boucle / hwopt-xilinx-7series · GitLab (at gricad-gitlab.univ-grenoble-alpes.fr) | 10:08 |
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| vancz | cool | 16:53 |
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