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| Adrien[m] | Hi ! I'm trying to synthesize a verilog component with yosys, for xilinx target. But I'm hitting a issue related to some defparam but there are nodefparam in the design... Is there any known issue about that in yosys ? | 14:59 |
|---|---|---|
| Adrien[m] | ZipCPU: it is your component `aximm2s`, looks very promising to experiment with hardware acceleration on Zynq :-) | 14:59 |
| Adrien[m] | I've created a small archive with the code. note that the top-level is generated by ghdl. just type make. https://cloud.univ-grenoble-alpes.fr/s/zjjt8PpimRdzjxs | 15:04 |
| tpb | Title: Cloud UGA (at cloud.univ-grenoble-alpes.fr) | 15:04 |
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| Adrien[m] | Here is the error message :... (full message at <https://catircservices.org/_irc/v1/media/download/AYp-PFsZD0ZoBVV6EzJ3ERb5JY6YimZQbldEc4TBawrrZcoW0T-xsgUeZfTaz-WHj4gecKhEGfq12yo1FFI9Ate_8AAAAAAAAGNhdGlyY3NlcnZpY2VzLm9yZy9lU2xoVUZZVkFNdnl4eUlaWEZJZVhBV2M>) | 15:27 |
| ZipCPU | Hello, Adrien[m]. Yes, I have an aximm2s component. I imagine others may have built their own as well. You can find mine at https://github.com/ZipCPU/wb2axip/blob/master/rtl/aximm2s.v | 15:32 |
| ZipCPU | (Judging from your .tar.gz file, that's what you already have ...) | 15:37 |
| ZipCPU | I can't comment on whatever ghdl is up to (don't have the most recent version installed here ...), but yosys seems to have no problems with aximm2s on down--save one: you also need the sfifo.v file from wb2axip. | 15:39 |
| Adrien[m] | I provided the ghdl-generated verilog in the archive to ease reproducing the issue. I'll add sfifo.v and try again. | 15:41 |
| ZipCPU | Sorry, I just don't do much with VHDL, so I can't reproduce that part of your issue. | 15:45 |
| Adrien[m] | No improvement with sfifo.v added : Yosys is still complaining. I'm now using a freshly-compiled yosys. If the version you are using is older then I'm probably hitting a regression. | 15:48 |
| ZipCPU | Could be, but remember I'm also running from aximm2s.v on down, without touching the VHDL files. | 15:50 |
| Adrien[m] | What is most weird is that there is no defparam anywhere, even in the ghdl-generated code. That generated code is the simplest form of verilog imaginable so it's very easy to scan for dubious generate code - I found nothing... | 15:51 |
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| ZipCPU | Try this: Set the parameters of aximm2s explicitly, rather than overriding them. Remove the "generic" portion of the component declaration. See if that helps. | 15:53 |
| Adrien[m] | I think I have found the root cause, in the instantiation of aximm2s. Indeed coming from vhdl eases triggering that issue. Two parameters are (erroneously) set here, because they provide the size of some ports. But these are localparams in the aximm2s implementation, so setting these externally is forbidden, and the error message is misleading. | 16:05 |
| ZipCPU | o/ | 16:09 |
| ZipCPU | It would certainly be a Verilog error to try to override a localparam. | 16:10 |
| Adrien[m] | You did guide me in the right direction. Thanks ! | 16:11 |
| ZipCPU | You did all the work. Still, I'm glad I could help. | 16:11 |
| Adrien[m] | So we will use a slightly edited aximm2s to continue our experiments : convert these 2 localparams to parameters, so they can be declared in vhdl side, and be referenced in port declarations. That'll do for now. | 16:13 |
| Adrien[m] | I've got a real question for you, though : have you already worked with Zynq-7000 SoC ? It uses AXI3. So initially we thought to experiment with axi32axi and axi3axi3 but comments indicate these are not really finished or validated. | 16:18 |
| Adrien[m] | So I thought we could try modified aximm2s and axis2mm to just cap the burst length to 16, the rest should be compatible. Are there reasons to believe this may not work ? | 16:19 |
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| ZipCPU | Adrien[m]: That's pretty close to what you might need to do. | 16:22 |
| ZipCPU | The issue with conversion from AXI4 to AXI3 is that ... I haven't gotten the logic working (yet) to convert bursts to smaller burst sizes. | 16:23 |
| ZipCPU | However, if you just limit the burst size to 16 beats you are then over halfway there. | 16:23 |
| ZipCPU | You'll also want to set both bits of AxLOCK to zero. (AXI3 has a two bit AxLOCK value) You're likely to want to double check the AxCACHE bits. | 16:24 |
| ZipCPU | Oh, and you'll need to set WID to the AX_ID used by the MM2S controller. | 16:24 |
| ZipCPU | Those should be all the updates you need. | 16:24 |
| ZipCPU | (Why AxCACHE? Because the meaning of that bit-field changed between AXI3 and AXI4 as I recall.) | 16:25 |
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| orhosko | hello everyone, | 17:49 |
| orhosko | I'm trying to create a byte/halfword/word addressable bsram for tangnano20k. I both tried 32 bit memory and 8 bit one. 32 bit one fails when addr%4==1 etc. since it requires to access more than 1 word at the same time. And 8 bit based cannot be synthesized I'm not sure why. Do you have any ideas or some example. Or is it just not possible? | 17:49 |
| orhosko | Here is my code if it helps: | 17:49 |
| orhosko | ``` | 17:49 |
| orhosko | (* ram_style = "block" *) // errors if not possible | 17:49 |
| orhosko | logic [7:0] mem[2**12]; // 4KB example | 17:49 |
| orhosko | logic [3:0] write_enable; | 17:49 |
| orhosko | always_comb begin | 17:49 |
| orhosko | case (fn3) | 17:49 |
| orhosko | `FN3_SB: write_enable = 4'b0001; | 17:49 |
| orhosko | `FN3_SH: write_enable = 4'b0011; | 17:49 |
| orhosko | `FN3_SW: write_enable = 4'b1111; | 17:49 |
| orhosko | default: write_enable = 4'b0000; | 17:49 |
| orhosko | endcase | 17:49 |
| orhosko | end | 17:49 |
| orhosko | logic [31:0] rdata; | 17:49 |
| orhosko | integer i; | 17:49 |
| orhosko | always @(negedge clk) begin | 17:49 |
| orhosko | I broke the for part while pasting. It should be | 17:51 |
| orhosko | ``` | 17:51 |
| orhosko | always @(negedge wclk) begin | 17:51 |
| orhosko | rdata <= 0; | 17:51 |
| orhosko | for (i = 0; i < 4; i = i + 1) begin | 17:51 |
| orhosko | if (write_enable[i] && wr_en) mem[_addr_in+i] <= data_in[8*i+:8]; | 17:51 |
| orhosko | rdata[8*i+:8] <= mem[_addr_in+i]; | 17:51 |
| orhosko | end | 17:51 |
| orhosko | end | 17:51 |
| orhosko | ``` | 17:51 |
| janrinze | orhosko: do you really want negedge there? | 17:54 |
| orhosko | janrinze: all the other part uses posedge, it is single cycle core and it is working in a simulation only that way. Is it that bad a thing?:/ | 17:56 |
| janrinze | orhosko: why not double the frequency and have it a dual cycle CPU? | 17:57 |
| orhosko | If this is not possible it will be the only solution i guess | 17:58 |
| janrinze | anyway, it seems like you are making it way more complicated than it is. You probably want to do byte access, halfword access and word access. | 17:58 |
| janrinze | byte access usually allows for all sequential bytes, not just the bottom byte of the 32 bit word. | 17:59 |
| janrinze | Do you only want to access the bottom byte? | 17:59 |
| orhosko | isn't this byte address, I'm not sure how can i simplify | 18:00 |
| janrinze | well your example writes to a bottom byte, bottom half word or a word. Right? | 18:00 |
| janrinze | Ah.. you are trying to have a byte wide memory to do 4 writes in one go with word writes! | 18:01 |
| orhosko | I don't think so word size 32 but I use byte addressing. | 18:01 |
| orhosko | yes exactly | 18:01 |
| janrinze | that requires 4 write ports to the same memory. | 18:02 |
| orhosko | so being not synthesizable was correct | 18:02 |
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| orhosko | if I made it 32 bit wide it would still require 2 write ports right? not correctly alligned writes would access 2 words | 18:03 |
| orhosko | and i believe it would require more logic | 18:04 |
| janrinze | yes that could work. | 18:04 |
| orhosko | I'm not sure whether 2 write ports is allowed though | 18:04 |
| janrinze | you can have true dual-port RAM that allows 2 ports | 18:04 |
| janrinze | so that will work. | 18:04 |
| janrinze | is the CPU your own design or has it a known ISA? | 18:05 |
| orhosko | it is riscv i should have mentioned that too... | 18:06 |
| orhosko | is there a good resource that you know | 18:06 |
| orhosko | is true dual-port RAM supports 2 write + 1 read. That would be 3 ports. | 18:06 |
| janrinze | RISC-V can do byte access.. just use the proper write flags from the RISC-V | 18:06 |
| janrinze | read/write can be done on one port | 18:07 |
| orhosko | im not sure what would be the proper flags. | 18:07 |
| janrinze | true dual-port can do read and write on port 1 , read and write on port2 | 18:08 |
| orhosko | >read/write can be done on one port | 18:09 |
| orhosko | then still i cannot write a word to not word alligned address. I am not sure if it is required in the specification. If not this will be the best solution for my case ig. | 18:09 |
| janrinze | normally there is are 4 byte select bits. the CPU will choose which bytes from the 32 bit word are written to. | 18:09 |
| orhosko | i didn't understand:( | 18:10 |
| janrinze | I don't know if RISC-V actually allows non-word aligned word-access. Most CPUs would read 2 words sequentially and then shift it to align. | 18:10 |
| janrinze | a 32 bit bus to memory would have 4 signals to let the memory know which byte will be written to. | 18:13 |
| orhosko | ok it make sense. a quick search says it is not mandatory to support non-word aligned word-access. | 18:13 |
| janrinze | https://github.com/ultraembedded/riscv/blob/master/core/riscv/riscv_core.v the ouput mem_d_wr_o is 4 bits. one for each byte | 18:15 |
| janrinze | The CPU should handle the non-word aligned access. Not the memory. | 18:15 |
| orhosko | so byte access will be write_enable = 1 << _addr_in[1:0] kind of thing. | 18:15 |
| orhosko | halfword similarly | 18:15 |
| orhosko | word access split to 2 words is not necessary. if I understanded correctly. | 18:15 |
| janrinze | actually the address should be in words, the byte lanes are each one bit. | 18:16 |
| orhosko | > The CPU should handle the non-word aligned access. Not the memory. | 18:17 |
| orhosko | This really make sense I have been trying to create a bad abstraction happen for hours | 18:17 |
| janrinze | but yes, if you want to handle it in the memory you need the bottom two bits. | 18:17 |
| janrinze | that last line referred to the bytelanes. not to your last comment | 18:18 |
| orhosko | > actually the address should be in words | 18:18 |
| orhosko | isnt riscv byte addressable. the other way seems way harder | 18:18 |
| janrinze | the CPU can do byte access.. it will select the right byte from the word. | 18:18 |
| orhosko | kinda meaningless question i know but which one do you recommend | 18:19 |
| janrinze | the memory itself is 32 bit. | 18:19 |
| orhosko | byte addressable memory or selecting correct parts from the 32 bit memory | 18:20 |
| janrinze | use 32 bit access and use the 4 byte select. | 18:20 |
| orhosko | thank you so much it really makes sense. | 18:20 |
| janrinze | :-) | 18:21 |
| orhosko | ummm, last question, how can i make byte load into word sized memory in single cycle | 18:23 |
| orhosko | if i load 32 bits wouldnt it overwrite other parts | 18:23 |
| janrinze | only write to the bytes that are selected. not the whole 32 bit word. | 18:27 |
| orhosko | my brain melted i guess. somehow i thought when 32 bit wide bsram created it can only load 32 bits and there is no masking capability | 18:29 |
| janrinze | if (w_lane0) mem[addr][7:0]<= data[7:0]; if (w_lane1) mem[addr][15:8]<=data[15:8] .. etc. | 18:29 |
| janrinze | the w_laneX is the mask! | 18:29 |
| orhosko | but will this synthesized or require 4 ports again | 18:30 |
| janrinze | always @(negedge wclk) begin | 18:32 |
| janrinze | for (i = 0; i < 4; i = i + 1) begin | 18:32 |
| janrinze | if (write_enable[i] && wr_en) mem[_addr_in>>2][8*i+:8] <= data_in[8*i+:8]; | 18:32 |
| janrinze | end | 18:32 |
| janrinze | rdata <= mem[_addr_in]; | 18:32 |
| janrinze | end | 18:32 |
| janrinze | oops rdata <= mem[_addr_in>>2]; | 18:33 |
| janrinze | and make mem 32 bits wide. | 18:33 |
| janrinze | the CPU should figure out which byte it wanted to read.. | 18:34 |
| janrinze | I hope this is not a home-work assignment ;-) | 18:34 |
| orhosko | no lol. just nerd-sniped from my friend. he bought the fpga and we are trying to create our own core. | 18:35 |
| janrinze | the write_enable bits are the same bits as the mem_d_wr_o in the link. | 18:39 |
| orhosko | I'm currently testing | 18:40 |
| orhosko | (* ram_style = "block" *) // errors if not possible | 18:40 |
| orhosko | logic [31:0] mem[2**12]; // 4KB example | 18:40 |
| orhosko | logic [3:0] write_enable; | 18:40 |
| orhosko | always_comb begin | 18:40 |
| orhosko | case (fn3) | 18:41 |
| orhosko | `FN3_SB: write_enable = 1 << (_addr_in[1:0]); | 18:41 |
| orhosko | `FN3_SH: write_enable = 3 <<(_addr_in[1:0]); // TODO: check misallignment | 18:41 |
| orhosko | `FN3_SW: write_enable = 4'b1111; | 18:41 |
| orhosko | default: write_enable = 4'b0000; | 18:41 |
| orhosko | endcase | 18:41 |
| orhosko | end | 18:41 |
| orhosko | logic [31:0] rdata; | 18:41 |
| orhosko | integer i; | 18:41 |
| orhosko | always @(negedge wclk) begin | 18:41 |
| orhosko | for (i = 0; i < 4; i = i + 1) begin | 18:41 |
| orhosko | if (write_enable[i] && wr_en) mem[_addr_in>>2][8*i+:8] <= data_in[8*i+:8]; | 18:41 |
| orhosko | end | 18:41 |
| orhosko | last part is wrong i noticed that now. | 18:43 |
| orhosko | probably i tried like this earlier and got frustrated then switched to 8 bit wide | 18:43 |
| orhosko | it should select depending onto address | 18:44 |
| janrinze | usually we don't post multi-line comments like this but use links to files as in https://bpa.st/ and add the link here. | 18:44 |
| tpb | Title: Create new paste (at bpa.st) | 18:44 |
| orhosko | > usually we don't post multi-line comments like this but use links to files as in https://bpa.st/ and add the link here. | 18:46 |
| orhosko | ohh, sorry i didn't know that | 18:46 |
| tpb | Title: Create new paste (at bpa.st) | 18:46 |
| janrinze | see here: https://bpa.st/LRTQ | 18:49 |
| tpb | Title: View paste LRTQ (at bpa.st) | 18:49 |
| janrinze | orhosko: it's the nettiquette to use links. That way we don't spam the channel. | 18:52 |
| janrinze | the link https://bpa.st/LRTQ has a small fix for the half-word read and adds the actual read. | 18:53 |
| tpb | Title: View paste LRTQ (at bpa.st) | 18:53 |
| janrinze | orhosko: Do you use github? Tha might be easier too. | 18:54 |
| orhosko | janrinze: i should have guessed you are right. https://github.com/orhosko/fpga-core/tree/memory is the github | 18:57 |
| orhosko | but i havent pushed yet | 18:57 |
| orhosko | https://bpa.st/555Q is the current code | 18:58 |
| tpb | Title: View paste 555Q (at bpa.st) | 18:58 |
| janrinze | I see you added a method to realign the reads. nice. | 19:02 |
| orhosko | it synthesize but seems like i have some logic errors in other places | 19:05 |
| orhosko | thank you for everything | 19:06 |
| janrinze | orhosko: I think your issues are not yosys related. perhaps you want to move to #verilog ? | 19:06 |
| janrinze | orhosko: you're welcome. :-) always nice to help out. | 19:06 |
| orhosko | janrinze actually i should have stop im missing my bus | 19:06 |
| orhosko | thank you again | 19:07 |
| orhosko | good evening | 19:07 |
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| janrinze | while i'm here I might just as well ask: can a pcf file have the drive strength for a pin for HX8K? | 19:11 |
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| whitequark[cis] | HX8K does not have configurable drive strength | 23:05 |
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