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| vup[m] | Catherine: in `cxxrtl`, two back to back `.step()` should not change the value of output ports, right? | 17:45 |
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| whitequark[cis] | not unless there is a bug somewhere | 17:47 |
| whitequark[cis] | are you using submodules or black boxes? | 17:47 |
| vup[m] | nope | 17:47 |
| whitequark[cis] | any feedback arcs? | 17:48 |
| whitequark[cis] | do you get convergence on the first delta? | 17:48 |
| vup[m] | (assuming with submodules you mean -noflatten) | 17:48 |
| whitequark[cis] | yes | 17:49 |
| vup[m] | no feedback arcs, but I do a splitnets -driver; clean -purge because I get them otherwise | 17:49 |
| whitequark[cis] | does it work if you skip splitnets? | 17:49 |
| vup[m] | whitequark[cis]: with splitnets yes | 17:52 |
| vup[m] | whitequark[cis]: yes | 17:52 |
| whitequark[cis] | right | 17:52 |
| whitequark[cis] | is the netlist weird somehow or is it just normal? | 17:52 |
| whitequark[cis] | i realize this is a very subjective thing | 17:53 |
| whitequark[cis] | oh, any clocks generated by logic? | 17:53 |
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| vup[m] | no, no clocks generated by logic | 17:54 |
| vup[m] | but I think you could say its a weird netlist. Its (partly) vhdl synthed by ghdl with a "weird" codestyle. | 17:54 |
| vup[m] | take this for example: https://paste.niemo.de/raw/mopehuhoru | 17:56 |
| vup[m] | ghdl makes internal_bus a single very wide signal, which is the source of all the feedback arcs... | 17:57 |
| vup[m] | s/mopehuhoru/seweseteyi/ | 17:58 |
| vup[m] | vup[m]: (updated the link to have a more self-contained example) | 17:58 |
| whitequark[cis] | that doesn't seem unreasonable | 18:06 |
| whitequark[cis] | if you have an MCVE as an RTLIL netlist feel free to submit an issue at least | 18:06 |
| whitequark[cis] | RTLIL + C++ driver | 18:06 |
| vup[m] | will do | 18:07 |
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