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| Adrien[m] | It was not straightfoward, my notes could be interesting to others | 13:53 |
|---|---|---|
| Adrien[m] | And I'm also taking any suggestions to fix issues ! | 13:53 |
| Adrien[m] | Guys I've managed to do FPGA synthesis on-board... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/fyOJHkPyJQXTztySGTHhGvRL>) | 13:53 |
| juri_ | wow, that looks really good. :) | 14:59 |
| juri_ | thank you for this. :) | 14:59 |
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| Adrien[m] | Just though about it : a soft-core CPU could also be enough to run all suff actually in-FPGA and having an FPGA re-synthesize "itself". | 15:29 |
| Adrien[m] | Choose the CPU model wisely : need to run a GNU/Linux distribution to benefit from repositories of precompiled tools and dependencies. | 15:29 |
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| somlo | Adrien[m]: have a look at https://archive.fosdem.org/2023/schedule/event/rv_selfhosting_all_the_way_down/ (disclaimer: I'm the author :) | 16:02 |
| tpb | Title: FOSDEM 2023 - Self-Hosting (Almost) All The Way Down (at archive.fosdem.org) | 16:02 |
| Adrien[m] | Too bad this was in Risc-V devroom I would have seen this | 16:26 |
| somlo | I managed to talk my higher-ups into giving me a month of $dayjob to see if I can get this working on a xilinx board (i.e., using nextpnr-xilinx instead of vivado, to preserve the "self-hosting" property) | 17:08 |
| somlo | on the premise that one can build bigger/faster softcore SoCs on xilinx compared to Lattice ECP5 :) | 17:10 |
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| GenTooMan | good fortune with that is all I can say | 18:23 |
| GenTooMan | may you not be cursed by crazed support information and arbitrary patches to dead versions of linux. | 18:24 |
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| Adrien[m] | My little experience is for now purely with Zynq boards Zybo and Zedboards, respective FPGA size is 17k and 54k LUT6. RAM size is 512 MB (off-chip DDR). | 20:12 |
| Adrien[m] | My observation is that the limit is the amount of RAM available for the place-and-route tools. With 512 MB for the entire system, only a small fraction of the Zybo board can be used... this constraint should be largely relaxed with some Kintex boards with a few GBs of on-board RAM. | 20:12 |
| Adrien[m] | Yosys also takes a lot of RAM depending on the design size and also depending on some internal shape of the design, not sure what exactly | 20:13 |
| somlo | Adrien: IIRC, zynq based boards can only access RAM through the hard-IP (arm?) cpu core, so I've been avoiding any "hybrid" hard-cpu + fpga combos | 20:15 |
| somlo | I'm looking at the nexys video (artix7), genesys2 (kintex7), or some virtex7 board with a SODIMM socket where the soft-IP memory controller can talk directly to the DRAM | 20:17 |
| juri_ | somlo: according to my reading of the datasheet, the memory controller is accessable from both the Arm cores, and the fpga. | 20:22 |
| Adrien[m] | Yes Zynq boards have the RAM accessible through the memory controller embedded in the PS part of the chip (Processor Subsystem), so it's completely part of the ASIC part of the chip. | 20:23 |
| Adrien[m] | For performance and energy it's great, and about resource usage it provides high bandwidth for both CPU and FPGA with absolutely no FPGA usage overhead taken by the DDR interface. | 20:23 |
| Adrien[m] | I think the ZC706 has 1GB of RAM as an SODIMM, should be upgradable, and the FPGA is large (but bitstream not documented in prjxray) | 20:23 |
| Adrien[m] | I mention the ZC706 only because it would complete so nicely the set of Zynq boards and chips tested with that flow | 20:25 |
| Adrien[m] | Correction : it has 1GB connected on PS memory controller, and 1GB directly on the FPGA. | 20:26 |
| Adrien[m] | * the FPGA. Total 2GB. | 20:26 |
| Adrien[m] | somlo: virtex7 bitstream is not documented yet in prjxray so no short-term hope about "self-hosting" these chips. | 20:29 |
| Adrien[m] | I have a VC709 board with 8GB of RAM and would like so much to materialize this... | 20:29 |
| juri_ | what will we need to do to get the larger zynq chips supported? poking a 7045 at the moment... | 20:45 |
| somlo | I could probably work on understanding prjxray itself, and see if there's something that could be done about virtex7 (I have access to a vc707 board, but I don't think physical hardware is actually needed for prjxray, just ability to run the vendor toolchain *a lot* :) | 20:50 |
| Adrien[m] | Either this chip was too large (233k LUT6) to make it a priority for bitstream documentation. | 20:52 |
| Adrien[m] | Or, it did not exist yet in Vivado 2017.2 which is still the only supported version (see https://github.com/f4pga/prjxray/issues/14) | 20:52 |
| Adrien[m] | (about the xc7z045) | 20:53 |
| Adrien[m] | (correction 218k LUT6) | 20:53 |
| juri_ | it does look rather nice. :) | 20:54 |
| somlo | so, create a vm template based on some ancient debian/ubuntu/fedora, hack it to work with 2017.2, and launch as many instances as the underlying hardware will support :) | 20:57 |
| somlo | for a prjxray n00b, it might be the path of least resistance (as compared to "dig in and fix issue #14 the Right Way (tm)") :D | 20:58 |
| juri_ | where can i even grab 2017.2 now? looks like all links point into login.amd.com | 20:59 |
| somlo | there's mention of some archive in one of the replies (but maybe you already tried that and got the dead login page ?) | 21:00 |
| juri_ | yep. | 21:00 |
| somlo | oh well, then, there's always the "Maximum Effort" option :D | 21:00 |
| Adrien[m] | For now the 2017.2 can still be run easily on recent distros, just need compat libs for ncurses5 and libxcrypt or something. | 21:02 |
| Adrien[m] | The old versions of vivado can still be downloaded, select "Vivado archive" on the left : | 21:02 |
| Adrien[m] | https://www.xilinx.com/support/download.html | 21:02 |
| juri_ | that's where i was. | 21:03 |
| Adrien[m] | The only issue about versions beyond 2017.2 seems to be vivado refusing to handle design that places LUT6_2 immadiately followed by a MUXF in the same slice. Supposedly this would have no practical usefulness. So some fuzzers fail. But I'm fairly convinced that just skipping potentially problematic fuzzer designs would still let the whole fuzzing system document most of the FPGA, if not everything. Just nobody pushed the effort up to porting | 21:14 |
| Adrien[m] | the entire prjxray to any other version. | 21:14 |
| Adrien[m] | Not claiming old FPGAs supported by 2017.2 should be converted to another version of Vivado. | 21:15 |
| Adrien[m] | IMHO having even partially documented bistreams for Virtex-7 and all other Kintex and Artix and Zynq chips is a better beginning than having no support at all. | 21:15 |
| Adrien[m] | Take care a vivado 2023 install is 110-180GB of disk space depending on what is selected... | 21:16 |
| somlo | juri_: presumably if you had (or created) an AMD/Xillinx account, you could then grab a copy? I'll have to try that myself... | 21:22 |
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| whitequark[cis] | vivado always required a xilinx account to download, for export control reasons | 21:25 |
| whitequark[cis] | i recall getting one in 2017, i think | 21:25 |
| Adrien[m] | somlo: I added links to your web page and FOSDEM presentation to related works in my little repo ;) | 21:26 |
| somlo | Adrien[m]: Thanks! Hope it ends up being useful :) | 21:30 |
| somlo | should definitely be more useful if it can run on a larger/faster FPGA than Lattice ecp5 | 21:31 |
| Adrien[m] | To give you figures, genarating a bitstream for an AES core (something like 1000-2000 LUT6 ?) takes around half an hours for my intern. When he's done his repo will be available public too with all details, not sure when, if you are interested I can take a few more notes of our discussions. | 21:37 |
| Adrien[m] | There are many technology details in your works that I want to have a look at, the Rocket chip (or CVA6 more common nearby me), Fedora, soft cores, Litex, ... | 21:37 |
| Adrien[m] | (disclaimer : with baby to take care of and a part-time nurse, only part-time work time remains available for me ':) ) | 21:39 |
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| juri_ | ok, they do still offer it. | 22:09 |
| juri_ | it's just a royal pain. :D | 22:09 |
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| somlo | Adrien[m]: the full "assembly instructions" are at https://github.com/litex-hub/linux-on-litex-rocket | 22:45 |
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