Friday, 2024-04-26

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Guest59From the documentation, yosys is able to "Conversion of full-featured Verilog to simple Verilog". How can i do this? In particular i am interested in only unrolling generate loops.15:08
Guest59i've tried read_verilog in.v; hierarchy -top top; proc; write_verilog out.v15:10
Guest59But the output is too different from the input.15:10
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whitequark[cis]"only unrolling generate loops" isn't a feature yosys is offering15:14
whitequark[cis]what that documentation line means is that yosys can convert arbitrary verilog to "structural verilog"15:14
whitequark[cis]unfortunately "structural verilog" isn't any more well-defined than "simple verilog", so it's just confusing all around15:15
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Guest59the fact that yosys produces structural-verilog answers my question, thanks15:20
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whitequark[cis]perhaps that doc should be amended then16:23
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