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Guest59 | From the documentation, yosys is able to "Conversion of full-featured Verilog to simple Verilog". How can i do this? In particular i am interested in only unrolling generate loops. | 15:08 |
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Guest59 | i've tried read_verilog in.v; hierarchy -top top; proc; write_verilog out.v | 15:10 |
Guest59 | But the output is too different from the input. | 15:10 |
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whitequark[cis] | "only unrolling generate loops" isn't a feature yosys is offering | 15:14 |
whitequark[cis] | what that documentation line means is that yosys can convert arbitrary verilog to "structural verilog" | 15:14 |
whitequark[cis] | unfortunately "structural verilog" isn't any more well-defined than "simple verilog", so it's just confusing all around | 15:15 |
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Guest59 | the fact that yosys produces structural-verilog answers my question, thanks | 15:20 |
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whitequark[cis] | perhaps that doc should be amended then | 16:23 |
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