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| darkling | Neophyte question: Is there any good documentation on how to actually use yosys? The docs aren't exactly brimming with information, and I've found one "tutorial" that doesn't explain anything, just gives a couple of commands ex cathedra. | 20:40 |
|---|---|---|
| lofty | darkling: have you read the manual and/or the command reference? | 20:58 |
| lofty | https://yosyshq.readthedocs.io/projects/yosys/en/latest/ and https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd_ref.html | 20:58 |
| tpb | Title: Yosys manual (at yosyshq.readthedocs.io) | 20:58 |
| darkling | I've read the manual. It gives one example of a script. The command reference is just that... reference, not tutorial. | 20:58 |
| lofty | what are you trying to do? use it to synthesise for an FPGA? | 20:59 |
| darkling | I'd like to simulate first, and then synthesise. | 20:59 |
| lofty | for simulation, consider something like icarus verilog or verilator | 21:00 |
| darkling | So I can't use yosys as a single all-in-one solution? | 21:01 |
| lofty | there technically is `sim`, but I've never used it or seen anybody directly use it | 21:01 |
| lofty | and there's also write_cxxrtl, which builds a C++ simulation of your HDL | 21:02 |
| lofty | but whitequark would be the person to ask about that. | 21:02 |
| darkling | OK. Nevertheless, the yosys docs are distinctly impenetrable. It's landed straight in the usual failure mode of "here's all the things in alphabetical order", without explaining what the different types of things are, what the expected operational structures are, or how to fit them together in common use cases. | 21:03 |
| lofty | Okay. | 21:06 |
| lofty | So, the manual talks about script-based synthesis flows, which is how Yosys is typically used | 21:06 |
| lofty | at its core, Yosys represents the netlist as RTLIL | 21:07 |
| lofty | and all the commands are passed to operate or transform that RTLIL | 21:07 |
| darkling | I got the overall idea -- that you're passing netlists from one stage to the next. | 21:07 |
| lofty | There are no explicit stages. | 21:08 |
| darkling | Other than the one example script, there's nothing about how you should put things together, what steps you might want to take for different situations, what order they'd be useful to run in... | 21:08 |
| lofty | have you looked at something like synth_ecp5? | 21:09 |
| darkling | Not relevant for me -- I don't have that hardware. (I've got an Ice40, and a Xilinx6 in a SpecNext -- and I need to track down the docs on that latter one to work out how it's put together) | 21:10 |
| lofty | but as an example of how you should put things together, it is absolutely relevant to you | 21:11 |
| lofty | Hell; I wrote synth_intel_alm, and I can directly answer every question you have about what that script does | 21:11 |
| darkling | I still don't understand why the individual pieces of that are put together like that. | 21:13 |
| lofty | would you like me to walk you through how it works? | 21:13 |
| darkling | Or, if I don't need to know that, then what are the higher-level elements such as synth_ecp5 that I should be looking at? | 21:14 |
| lofty | the user-facing scripts are the `synth_xxx` passes | 21:14 |
| darkling | It seems that there's a bunch of low-level things (used in the ecp5 synth), but then those are combined into high-level things (like ecp5). | 21:15 |
| lofty | yes. | 21:15 |
| darkling | Those are thrown together in the docs without highlighting which pieces are which. | 21:15 |
| darkling | So, again, we come back to: what should someone be using, and how? | 21:15 |
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| darkling | Even "<lofty> the user-facing scripts are the `synth_xxx` passes" is an important piece of information that I didn't see in the docs. | 21:16 |
| darkling | I know I'm being grumpy about this, and I'm sorry, but it's a general problem in docs that I see frequently, and it's been annoying me for at lesat 20 years. :) | 21:17 |
| lofty | for ice40, use `yosys -p "synth_ice40 -top <your top-level modules> -json filename.json" <your verilog files>`, for xilinx use `synth_xilinx -flatten -top <your top level module> -json filename.json` instead of `synth_ice40` | 21:17 |
| darkling | Why is there -flatten in the xilinx one, but not in the ice40? | 21:18 |
| lofty | because for maintainer-related reasons, xilinx does not flatten the module hierarchy when everybody else does | 21:19 |
| lofty | (by default, I mean) | 21:19 |
| lofty | and nobody seems to use synth_xilinx enough to complain about that annoyance | 21:20 |
| darkling | OK. :) | 21:21 |
| lofty | actually, I should be more specific | 21:21 |
| lofty | you also need `-family xc6s` to instruct the pass to synthesise for spartan 6 | 21:21 |
| darkling | I'm a long way off being anywhere near needing to target the SpecNext. I'm still at the stage of two buttons, and AND gate, and an LED. :) | 21:22 |
| darkling | But I'll keep that in mind. | 21:22 |
| lofty | (I think the distinction between xc7 and xc6s from a synthesis point of view is the DSPs, but don't quote me on that) | 21:23 |
| lofty | I would be genuinely happy to explain how the synthesis scripts work, if you're interested | 21:24 |
| darkling | The "tutorial" I've found is https://eecs.blog/lattice-ice40-fpga-icestorm-tutorial/, and that uses arachne for place-and-route, and some chip-specific tooling for generating and uploading the bitstream. Is that normal procedure? | 21:24 |
| lofty | arachne-pnr is horrendously obsolete; you should use nextpnr-ice40 instead | 21:25 |
| lofty | but uploading generally has some kind of chip-specific tooling in some way | 21:25 |
| darkling | Not unexpected, but good to have confirmation. | 21:27 |
| darkling | Oh, and thanks for the offer on explanation of the synthesis scripts, but it's probably a step too far for me right now. | 21:28 |
| darkling | I'm sure I'll be back with those questions at some point, but right now if I can get two buttons and an LED working, it'll be a major advance for me. | 21:29 |
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