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Zevv | What's the typical procedure to optimize my design for size, what's an efficient method of finding out where the luts are being used? | 18:51 |
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lofty | Zevv: a good place to start is to use `-noflatten` to synthesise the logic hierarchically, which tells you which modules are contributing the most logic | 19:42 |
Zevv | thanks, lemme check that | 19:47 |
Zevv | right, that's nice | 19:49 |
Zevv | good. good. Is there a proper place on IRC to ask generic verilog questions? I'm past the total noob level I guess, but still have a lot to learn. | 20:04 |
lofty | Zevv: #fpga? | 20:28 |
lofty | sorry, ##fpga | 20:28 |
Zevv | right, thanks. I checked #fpga but it was pretty empty | 20:28 |
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