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| singham | tnt: Thanks, I read the docs for the 3 tiles | 04:59 |
|---|---|---|
| singham | As a hello world, I want to assign the pin M12 to zero by editing asc file | 04:59 |
| singham | How do I figure out logic cell closest to pin M12 in iCE40HX8K? | 05:00 |
| singham | Also, how is the grid laid out? | 05:01 |
| singham | Thanks in advance | 05:01 |
| singham | Sorry, I meant assigning M12 pin to 1 | 05:04 |
| singham | An led is connected to M12 | 05:04 |
| singham | Basically, I want to store all values of LUT close to IO pin to 1 and connect via span interconnects to pad | 05:06 |
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| Myrl-saki | FWIW, form what I understand, doesn't HeAP do that for you? At least that's what I understood from the rationale. | 05:22 |
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| Myrl-saki | I just realized I replied exactly as you left lol | 05:32 |
| singham | sorry | 05:33 |
| singham | Can you please repeat? | 05:33 |
| Myrl-saki | singham: IIRC, you don't need to manually place the logic cell, because that's what HeAP's whole rationale is. | 05:33 |
| Myrl-saki | But I'm not 1000% sure. | 05:33 |
| Myrl-saki | (I'm relatively new to this.) | 05:33 |
| singham | What's HeAP? | 05:36 |
| singham | I wrote ramtest program for testing RAM on Olimex HX8K board | 05:37 |
| singham | and it is not working correctly | 05:37 |
| singham | I mean verilog program | 05:41 |
| singham | For ramtest, I believe I'd rather write asc directly and make FSMs on paper | 05:41 |
| Myrl-saki | HeAP is a placement algorithm which nextpnr also supports. | 05:43 |
| singham | I'm talking about writing asc by hand and then going to bitstream with icepack | 05:44 |
| singham | It doesn't concern nextpnr | 05:44 |
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| lofty | singham: I have to ask why you want to do this, because this is setting yourself up for misery. | 07:47 |
| singham | I find it simpler to do fsm and binary code than verilog | 07:48 |
| lofty | At least if you were using nextpnr you could still entirely manually place and route everything. | 07:48 |
| singham | Also, procedural things confuse me in HDL | 07:48 |
| singham | How do I figure out logic cell closest to pin M12 in iCE40HX8K? And assign it to 1 in asc file | 07:49 |
| lofty | which chip package? | 07:50 |
| singham | ct256 | 07:51 |
| lofty | M12 is X27/Y0/io1, so that would be X27/Y1/lc0 | 08:01 |
| lofty | singham: ^ | 08:01 |
| lofty | how do you assign it to 1? well, I would put a LUT4 in there with an all-ones LUT mask | 08:02 |
| singham | How to find that 27 0 is M12? | 08:14 |
| singham | Which logic cell is closest to it? | 08:15 |
| singham | 27 0 ? | 08:15 |
| singham | I mean 27 1? | 08:15 |
| lofty | singham: https://github.com/YosysHQ/icestorm/blob/master/icebox/icebox.py#L4883 | 08:23 |
| singham | lofty: Beautiful, beautiful! Thank you so much! | 08:23 |
| singham | Bow down to you | 08:24 |
| lofty | I still strongly urge you not to try to directly write an ASC from this | 08:25 |
| lofty | I could probably write your FSM faster than you could write the necessary infrastructure needed to do this manually | 08:26 |
| singham | How? | 08:28 |
| singham | :D | 08:29 |
| lofty | because the tooling already knows all of this, and is designed to make your life as easy as possible | 08:29 |
| singham | I don't think so. | 08:29 |
| lofty | you were asking how to make a logic cell emit a 1 | 08:29 |
| lofty | if you have to ask that, you probably don't presently possess the knowledge required to encode your logic in the hardware | 08:30 |
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| singham | Well, I'm an IITian and IIT students cover quite some ground in mere days | 08:43 |
| singham | Don't worry about that. All tools will be made as simple as possibly can and will be omitted altogether to help the user! | 08:44 |
| lofty | this is a recipe for burnout, I think. | 08:44 |
| singham | I mean I'd update and contribute if need be | 08:45 |
| singham | By default, it is not a state of burnout | 08:45 |
| singham | By default, our IITian's state of mind is energetic and independent | 08:46 |
| lofty | I think you completely misunderstood me there | 08:47 |
| lofty | I work for YosysHQ. I work on Yosys and nextpnr and the open tooling in general. | 08:47 |
| lofty | so, I would like to say I have a reasonably informed opinion on this topic. | 08:47 |
| singham | The only issue I find is help is scarce even amongst people who should align. See, we both want to improve coding FPGAs and so you helped me but normally, I don't find such co-operation | 08:47 |
| singham | Thanks again man! | 08:47 |
| lofty | don't get me wrong, I think Verilog is bad | 08:48 |
| lofty | but manually playing "connect the dots" on an FPGA will not scale for anything more than trivial tasks | 08:48 |
| lofty | people just do not have time for it | 08:48 |
| lofty | even if they did, nextpnr already supports that! | 08:48 |
| singham | Yeah, I too feel so many transistors aren't needed. | 08:48 |
| singham | I just have to implement a few instructions happening again and again like a processor | 08:49 |
| lethalbit | yeah, using a pnr tool is the best way, doing it manually is an exercise in madness and tbh likely a huge waste of time | 08:49 |
| lethalbit | trust lofty here, they know what they're talking about | 08:51 |
| singham | But when things don't work, it's even worse to find the issue in the code | 08:51 |
| singham | I mean verilog code | 08:51 |
| lofty | that's what simulators are for | 08:51 |
| lethalbit | ^^ | 08:51 |
| singham | Simulator and synthesis are different | 08:51 |
| lethalbit | Also you could use something else, like VHDL, or Chisle, et. al. | 08:51 |
| singham | With Synthesis, so many features are not even present | 08:52 |
| lofty | they are different, yes, but if your design simulates correctly it should synthesis correctly | 08:52 |
| jix | singham: there's post-synth simulation for that | 08:52 |
| lofty | or you could use a language which does not have such a difference in features between simulation and synthesis, like Amaranth or such | 08:52 |
| lethalbit | hi jix! it's been a while, hope you're doing well :3 | 08:53 |
| lofty | o/ jix | 08:53 |
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| singham | I thank you all | 09:02 |
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| jix | lethalbit: hi! sry went afk right after my last msg (and will again shortly)... can't complain overall ... your collab stream with lina the other day looks really cool from the short peek I had so far, meaning to watch it fully when I can finde the time, looks like it's at the right level and pace for me if I want to finally figure out magic and related stuff | 09:18 |
| lethalbit | it's all good~ | 09:19 |
| lethalbit | It's some really basic intro stuff, I wasn't able to go into a lot of details for questions that Lina asked as it got to the edge of my knowledge but I hope it's helpful enough for people just getting into it | 09:19 |
| lethalbit | I was also pretty sleepy during it so that doesn't help, but *shrug* | 09:20 |
| jix | well on the asic side I don't even know the basic stuff, I know some basic things in theory but never got around to use any of the tooling | 09:20 |
| lethalbit | Yeah, | 09:20 |
| lethalbit | the main issue imo is the tooling atm, OpenLANE is good, but for the manual cell layout magic is a mess and kinda janky and klayout is just not as capable so it's not a good replacment | 09:21 |
| lethalbit | so i'm poking on writing my own VLSI Layout tool that takes a bit after KiCads pcbnew so hopefully it'll be more useable :v | 09:22 |
| lethalbit | anywho, i've gotta crash, have a good one! | 09:22 |
| jix | the thing I saw so far was part of you showing how to actually use magic and the one time I wanted to do that in the past I didn't have the patience to figure that out | 09:22 |
| lethalbit | fair, magic is pretty hard to divine how to use | 09:22 |
| lethalbit | and even when you know how to use it, it's kinda moody | 09:22 |
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| singham | Folks | 19:41 |
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