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| st3llar | on ice40's EBR is it not possible to read and write on the same clock edge? | 09:43 |
|---|---|---|
| st3llar | doing so creates a bunch of extra luts and dffs | 09:43 |
| lofty | st3llar: what's the read vs write priority of your code? | 09:46 |
| lofty | Or in other words: if you read and write to the same address, does the read get the old data, the new data or is it undefined? | 09:48 |
| st3llar | oh, thought about that and so i tried different addresses, same result | 09:50 |
| st3llar | always @(posedge clk) begin mem[waddr] <= wdata; rdata <= mem[raddr]; end | 09:50 |
| lofty | st3llar: that's the source of the extra logic then; iCE40 doesn't natively support that so Yosys adds logic to catch and pass through values | 09:52 |
| tnt | If your design doesn't care about what happens if read and write at the same address occur (because either it doesn't matter or by design this will never occur), you can use the (* no_rw_check *) attribute on the memory. | 10:01 |
| st3llar | thanks! is this what's meant by *pseudo* dual port? | 10:01 |
| tnt | No. | 10:02 |
| st3llar | oh thanks for the tip | 10:02 |
| tnt | Pseudo dual port is because one port is read and the other is write. | 10:02 |
| tnt | (as opposed to some BRAM that can have two fully read/write ports). | 10:02 |
| st3llar | because i couldn't find any mention of the limit to read/write on the same clock edge in the datasheets, unless this is always the case? | 10:03 |
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