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| CanLehmann[m] | Is there a yosys pass for lowering tristate logic to boolean logic? (i.e. getting rid of all x and z values & replacing them with additional signals + cells) | 01:11 |
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| CanLehmann[m] | * of all **x and, * and z** values | 01:54 |
| CanLehmann[m] | <CanLehmann[m]> "Is there a yosys pass for..." <- It was pointed out to me on discord that the `tribuf` pass does this for `z` values. My usecase does however also require handling of `x` values. Is there anything that handles both? | 01:59 |
| CanLehmann[m] | * My usecase (building some RTL analysis passes) does however | 02:02 |
| CanLehmann[m] | * My usecase (building some RTL analysis passes) does however, * `x` values. Just defaulting them to 0/1 does not work. Is there | 02:04 |
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| jix | CanLehmann[m]: xprop can do this | 10:22 |
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| CanLehmann[m] | <jix> "Can Lehmann: xprop can do this" <- Thanks! `xprop -assume-def-inputs -split-outputs` seems to work quite well for registers. It does not seem to handle memories though. Is there any way to make it also split memories? | 18:01 |
| CanLehmann[m] | My current pass pipeline: proc; flatten; tribuf -formal; opt_expr; xprop -assume-def-inputs -split-outputs; opt_expr; opt_clean | 18:01 |
| jix | support for memories and submodules is still missing, depending on your use case you might get away with `memmory_map` before xprop, that will map the memory to dffs | 18:03 |
| jix | (and the -formal parameter to memory_map can also help if you're using it for verification/analysis and not actual synthesis) | 18:04 |
| jix | it doesn't get you the verilog simulation rules for x propagation though, which is what xprop uses for the builtin cells it does support | 18:05 |
| CanLehmann[m] | memory_map -formal seems to work in simple cases, however it does not scale well. | 18:09 |
| * CanLehmann[m] sent a code block: https://catircservices.org/_matrix/media/v3/download/catircservices.org/CPKJgpNsSvFlSIwrMbDZEhTF | 18:09 | |
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| jix | implementing memories using the verilog sim behavior (which ignores writes with x bits in addresses) would be possible, I just didn't get around to do that so far | 18:11 |
| CanLehmann[m] | CanLehmann[m]: > <@josh-leh:matrix.org> ```... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/zfMtqKwXGBhXPpKOoCNvtvCY>) | 18:11 |
| CanLehmann[m] | * My application is converting RTLIL to a custom IR for further analysis. I have a verilog backend for this custom IR and e.g. for this simple example, the size of the generated code is already 4780 LOC of verilog. | 18:12 |
| jix | implementing the behavior you get when mapping in a more efficient way isn't possible though as there x bits in addreses will write x bits to all matching addresse simultaneously which you cannot express using memory cells | 18:12 |
| CanLehmann[m] | Ah makes sense, I did not even think about x bits in addresses yet... | 18:13 |
| CanLehmann[m] | It might be simpler to "just" extend my custom IR to support unknown values in that case. | 18:13 |
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