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| FL4SHK | can yosys be made to use multiple CPU cores? | 14:35 |
|---|---|---|
| FL4SHK | I have 16 hardware threads... hoping to speed up the process | 14:35 |
| FL4SHK | (8 actual CPU cores) | 14:35 |
| tnt | FL4SHK: nope | 14:37 |
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| FL4SHK | tnt: that's unfortunate | 14:54 |
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| tnt | But how long can the synthesis be ? What are you doing ? | 14:55 |
| FL4SHK | I mean it takes a while because of how large my module is | 14:55 |
| tnt | yeah, but define what you consider "a while" and "how large" (which target ?) | 14:56 |
| FL4SHK | I'm only using yosys to try to get better results than Vivado | 14:57 |
| FL4SHK | the "target" is defined in Vivado | 14:57 |
| FL4SHK | it's an Arty A7 100T | 14:57 |
| FL4SHK | the number of lines of code is 100k but a lot of it is because it's generated by SpinalHDL | 14:58 |
| tnt | Mmm, ok, I see. | 14:59 |
| FL4SHK | okay this idea doesn't seem to be something that will work | 15:00 |
| FL4SHK | since even NeoVim can't open the synthesized .v file | 15:01 |
| FL4SHK | not with `proc` involved | 15:03 |
| FL4SHK | I'll try just `synth` | 15:05 |
| FL4SHK | what I'm hoping to achieve here is test whether yosys can figure out that I'm really doing a synchronous read from an array | 15:05 |
| FL4SHK | I am doing an asynchronous read from an array and passing the data to a pipeline skid buffer | 15:06 |
| FL4SHK | I was hoping yosys would be able to figure it out since Vivado doesn't | 15:06 |
| FL4SHK | otherwise I'll have to write fancier code that directly does synchronous reads from the array | 15:06 |
| FL4SHK | ...my goal is to infer BRAM | 15:06 |
| FL4SHK | since these arrays are rather large | 15:06 |
| FL4SHK | what I've made is a GPU for 2D graphics | 15:07 |
| FL4SHK | sprites and backgrounds | 15:07 |
| FL4SHK | very configurable and also open source | 15:07 |
| FL4SHK | it's in my libcheesevoyage library on my Githbu | 15:10 |
| FL4SHK | GitHub | 15:10 |
| FL4SHK | in the `hw/spinal/libcheesevoyage/gfx` directory | 15:10 |
| FL4SHK | my GitHub username is the same as my username here on IRC | 15:12 |
| FL4SHK | "fl4shk" | 15:12 |
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| Guest12 | anyone know how to simulate a verilog in yosys? | 15:21 |
| FL4SHK | Guest12: yosys isn't a simulator | 15:22 |
| FL4SHK | you need something like Verilator or Icarus Verilog for that | 15:22 |
| FL4SHK | also, for my problem, I have determined that yosys won't work for my situation | 15:23 |
| FL4SHK | so I'm going to implement something else | 15:24 |
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| Guest12 | FL4SHK then what's the point of yosys if verilator/icarus can directly simulate verilog? | 15:28 |
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| whitequark[cis] | synthesis | 15:35 |
| whitequark[cis] | that said, yosys does have a sim pass | 15:35 |
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| FL4SHK | oh it does? | 17:32 |
| FL4SHK | oops | 17:32 |
| FL4SHK | I forgot about CXX RTL | 17:32 |
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| whitequark[cis] | FL4SHK: no, CXXRTL and the `sim` pass are entirely independent | 19:08 |
| whitequark[cis] | so Yosys has two simulators in it | 19:08 |
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| FL4SHK | whitequark[cis]: gotcha | 20:57 |
| FL4SHK | that's very cool | 21:00 |
| FL4SHK | okay so yosys actually managed to synth_xilinx my feeding pipeline skid buffers with asynchronous reads to BRAM | 21:33 |
| FL4SHK | I had to use `synth_xilinx` for it | 21:37 |
| whitequark[cis] | what were you using before? | 21:58 |
| FL4SHK | Vivado | 21:58 |
| FL4SHK | its native synthesis | 21:58 |
| whitequark[cis] | ah | 21:58 |
| FL4SHK | Now I'm switching flow | 21:58 |
| FL4SHK | s | 21:58 |
| FL4SHK | this is excellent | 21:59 |
| FL4SHK | can I tailor the yosys to target specific Xilinx FPGAs? | 22:01 |
| FL4SHK | it appears that it's using UltraScale things | 22:04 |
| FL4SHK | but that's not what I have here | 22:05 |
| Wanda[cis] | you can choose the target family with `synth_xilinx -family <...>`; choosing specific FPGA is not supported | 22:13 |
| Wanda[cis] | it should be using series7 as the target by default | 22:13 |
| FL4SHK | family is fine with me | 22:13 |
| FL4SHK | oh | 22:14 |
| FL4SHK | but it output stuff that's apparently not available in series7 | 22:14 |
| FL4SHK | I'm working on adjusting my code | 22:14 |
| Wanda[cis] | what kind of stuff? | 22:14 |
| FL4SHK | RAM64M | 22:14 |
| Wanda[cis] | that's a valid 7 series primitive | 22:15 |
| FL4SHK | oh I see | 22:15 |
| FL4SHK | Xilinx's documentation didn't show it for 7 series | 22:16 |
| FL4SHK | Oh wait | 22:16 |
| FL4SHK | so it does | 22:16 |
| FL4SHK | my mistake! | 22:16 |
| Wanda[cis] | hm? | 22:16 |
| Wanda[cis] | I'm looking at UG768 (v14.7) and it's right there | 22:16 |
| FL4SHK | right | 22:16 |
| FL4SHK | I got linked to Ultrascale | 22:16 |
| FL4SHK | when I searched | 22:16 |
| FL4SHK | in any case | 22:17 |
| FL4SHK | that's not a design element I want to use | 22:17 |
| FL4SHK | I want to use fully block RAM | 22:17 |
| FL4SHK | so I'll be adjusting my code | 22:17 |
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