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| Butterkeks | I'm in need for an synthesis tool that can handle a mixed HDL design, my design is done in SystemVerilog and some base modules are in VHDL with multi-dimensional in/output signals. Thats the reason I switched for Simulation to Questa/ModelSim. | 14:31 |
|---|---|---|
| Butterkeks | But now I would like to get the gate-count and longest path delay. Does any one know some good tooling for this? | 14:31 |
| Butterkeks | I already found the yosys-UHDM and the yosys-GHDL plugin, does any one have experience in using them together? | 14:33 |
| Myrl-saki | I think the problem with my mux approach is that I'm using LUT3s as the input stage. I wonder if I can instead insert LUT1 buffers, build a MUX on top of those, and then let some optimization stage remove the LUT1s. | 14:36 |
| Myrl-saki | So MUX2 is LUT1 + LUT1 + MUX2_LUT5. | 14:36 |
| Myrl-saki | And then have some optimization stage merge those LUT1s Somewhere Else. | 14:36 |
| Myrl-saki | But then I think the problem is that tree depths are not necessarily preserved and other stuffs.... | 14:39 |
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