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| Myrl-saki | Is it unusual to use both clock edges? I'm designing my CPU such that it commits internally at negedge, while it interfaces with things at the posedge. | 14:57 |
|---|---|---|
| Myrl-saki | In hindsight though, the initial reasons kinda don't hold up lol | 14:58 |
| tnt | Yes, it's a bit weird. | 14:58 |
| tnt | Not unheard of but ... not that common. | 14:58 |
| jix | I think it used to be more common with latch based designs (although they often used two clock phases with the right amount of overlap I think?) but I don't know of a good reason to do it with dff based designs apart from matching existing interfaces that might use both edges... | 14:59 |
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| Myrl-saki | Thanks. :) | 15:07 |
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| Zaba | i've done some designs where the logic would be clocked on posedge but the outputs would be clocked on negedge so as to not worry about meeting setup/hold times when interfacing with things that latch their inputs on posedge | 16:50 |
| Zaba | but i'm not expert in this so i've no idea how much sense that actually made | 16:50 |
| crzwdjk | When I needed something like that (for SPI) I just inverted the output clock that goes to the external device. | 16:57 |
| tnt | yeah, using different edges for IO with the outside of the chip, that's pretty common. Either invert the output clock, capture on negedge ... or both ... whatever it takes to ensure you respect hold/setup times of whatever external device you talk to. | 17:00 |
| tnt | When the OP talked about "its interfaces", I understood it as "on chip interfaces, to other part of the fpga/asic" and not necessarily about external IO and so my answer is to take in that context. But I could of course have misunderstood, I hadn't even considered they could be talking about off-chip interfaces. | 17:02 |
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