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| povik | so I went over Andy's PR to create Booth multipliers | 15:15 |
|---|---|---|
| povik | https://github.com/YosysHQ/yosys/pull/3924 | 15:15 |
| povik | i want to merge it if there aren't any objections, with the promise that I will do a pass over the code after merging to clean it up a little | 15:16 |
| povik | Andy seems to have done the changes we requested in Monday's dev call | 15:17 |
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| mithro | I'm pretty sure I am doing something obviously wrong, but I'm not quite sure what - I'm getting these "hanging wires and buffers" in my `show` output despite calling `opt_clean` -- SystemVerilog code @ https://pastebin.ubuntu.com/p/tHXb5x2tZQ/ https://usercontent.irccloud-cdn.com/file/N33jSXJN/image.png | 22:00 |
| tpb | Title: Ubuntu Pastebin (at pastebin.ubuntu.com) | 22:00 |
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