| *** tpb <[email protected]> has joined #yosys | 00:00 | |
| *** GenTooMan <GenTooMan!~cyberman@2601:547:437f:e5c6:21f:5bff:fefe:a883> has quit IRC (Ping timeout: 248 seconds) | 04:23 | |
| *** GenTooMan <GenTooMan!~cyberman@2601:547:437f:e5c6:21f:5bff:fefe:a883> has joined #yosys | 04:24 | |
| *** bjorkint0sh <bjorkint0sh!~bjork@2600:1700:5400:c80:7974:7e94:9111:3ed3> has joined #yosys | 04:43 | |
| *** bjorkintosh <bjorkintosh!~bjork@user/bjorkintosh> has quit IRC (Ping timeout: 245 seconds) | 04:43 | |
| *** GenTooMan <GenTooMan!~cyberman@2601:547:437f:e5c6:21f:5bff:fefe:a883> has quit IRC (Ping timeout: 248 seconds) | 04:46 | |
| *** GenTooMan <[email protected]> has joined #yosys | 05:36 | |
| *** GenTooMan <[email protected]> has quit IRC (Ping timeout: 246 seconds) | 05:44 | |
| *** GenTooMan <GenTooMan!~cyberman@2601:547:437f:e5c6:21f:5bff:fefe:a883> has joined #yosys | 05:58 | |
| *** FabM <[email protected]> has joined #yosys | 06:21 | |
| *** cr1901_ <cr1901_!~cr1901@2601:8d:8600:226:bc7f:ccf1:49c0:41ee> has joined #yosys | 07:54 | |
| *** cr1901 <cr1901!~cr1901@2601:8d:8600:226:d523:f333:da88:b877> has quit IRC (Ping timeout: 248 seconds) | 07:55 | |
| *** nak <nak!~nak@yosys/nak> has quit IRC (Ping timeout: 246 seconds) | 10:20 | |
| *** nak <nak!~nak@yosys/nak> has joined #yosys | 10:22 | |
| *** lexano <[email protected]> has quit IRC (Ping timeout: 246 seconds) | 12:08 | |
| *** Guest96 <[email protected]> has joined #yosys | 13:17 | |
| *** Guest96 <[email protected]> has quit IRC (Client Quit) | 13:19 | |
| *** timkpaine <[email protected]> has joined #yosys | 14:00 | |
| *** timkpaine <[email protected]> has quit IRC () | 14:06 | |
| *** Scout <[email protected]> has joined #yosys | 14:11 | |
| *** Scout <[email protected]> has quit IRC (Client Quit) | 14:12 | |
| *** builderdev212 <[email protected]> has joined #yosys | 14:13 | |
| builderdev212 | I'm a bit new to yosys. I've used icarus/verilator to simulate verilog before and have played around with GHDL some, and have been looking into yosys because of the ghdl plugin. Is it possible to simulate both vhdl and verilog together? I've seen some work around simulating a vhdl module with a verilog top module, however the project i'm working to | 14:16 |
|---|---|---|
| builderdev212 | simulate has a verilog internal module that's called by my vhdl module. Is simulating this even possible? Or should I look into some other method of simulation? | 14:16 |
| *** derekn <[email protected]> has quit IRC (Ping timeout: 245 seconds) | 15:04 | |
| *** FabM <FabM!~FabM@armadeus/team/FabM> has quit IRC (Ping timeout: 246 seconds) | 15:10 | |
| *** derekn <[email protected]> has joined #yosys | 15:25 | |
| *** builderdev212 <[email protected]> has quit IRC (Quit: Client closed) | 15:56 | |
| *** cr1901_ is now known as cr1901 | 16:57 | |
| *** crzwdjk <[email protected]> has quit IRC (Ping timeout: 252 seconds) | 17:13 | |
| *** crzwdjk <[email protected]> has joined #yosys | 19:31 | |
| *** DX-MON <[email protected]> has quit IRC (Ping timeout: 252 seconds) | 20:54 | |
| *** lethalbit <lethalbit!~lethalbit@2001:19f0:7001:4da6:5400:1ff:fe66:6ca3> has quit IRC (Ping timeout: 240 seconds) | 20:54 | |
| *** MoeIcenowy <MoeIcenowy!~MoeIcenow@2401:c080:1000:445a:5400:4ff:fe31:6509> has quit IRC (Ping timeout: 246 seconds) | 20:55 | |
| *** crzwdjk <[email protected]> has quit IRC (Ping timeout: 248 seconds) | 20:58 | |
| *** DX-MON <[email protected]> has joined #yosys | 21:39 | |
| *** lethalbit <[email protected]> has joined #yosys | 21:40 | |
| *** MoeIcenowy <MoeIcenowy!~MoeIcenow@2401:c080:1000:445a:5400:4ff:fe31:6509> has joined #yosys | 21:41 | |
| *** crzwdjk <[email protected]> has joined #yosys | 21:47 | |
| *** nonchip <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.) | 22:16 | |
| *** nonchip <[email protected]> has joined #yosys | 22:16 | |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!