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| Guest35 | Hello! I'm trying to do a logic synthesis with yosys, but I don't understand how to make sdc. Examples don't have something which look like Genus "create_clock [get_ports "$CLK_PORT"] -name "$CLK_NAME" -period 40 -waveform {0 20}". How to check my frequency in project? I'm sorry if this channel is not for asking questions like mine, but I really | 11:16 |
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| Guest35 | want to understang how works Yosys for my university project. Thank you :] | 11:16 |
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