Wednesday, 2023-06-14

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fayalalebrunHello, I'm learning formal verification using GHDL, PSL, and Simbiyosys. I was wondering why the following code fails the induction step:12:33
fayalalebrunf_reset : assume {reset_in};12:33
fayalalebrunf_no_reset : assume next (always not reset_in);12:33
fayalalebrunf_no_reset_a : assert next (always not reset_in);12:33
fayalalebrunMy intent is to assume reset is only asserted at the start of the trace. Why would the assertion here fail? Do assumptions not apply during induction?12:33
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schaegIs some aware of any open source code base in Verilog-A, Verilog-AMS or VHDL-AMS (where the A isn't just for decoration)? Is someone aware whether one can write an VHDL/Verilog-AMS code in a foundary portable way?14:34
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so-offishOh I figured it out btw (the "Cell type is unsupported") :D20:59
so-offishThere was an error higher up (bad RTL) and once I fixed that we were handy dandy.20:59
so-offishSorry that was lame. "once I fixed that, it worked"20:59
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