| *** tpb <[email protected]> has joined #yosys | 00:00 | |
| *** FabM <FabM!~FabM@2a03:d604:103:600:2e60:8c7c:e8fb:7990> has joined #yosys | 06:06 | |
| *** cr1901 <cr1901!~cr1901@2601:8d:8600:911:4086:1792:10fb:d16> has quit IRC (Quit: Leaving) | 06:46 | |
| *** cr1901 <cr1901!~cr1901@2601:8d:8600:911:6198:7d26:5f37:f25a> has joined #yosys | 06:48 | |
| *** anticw <[email protected]> has quit IRC (Remote host closed the connection) | 07:38 | |
| *** anticw <[email protected]> has joined #yosys | 07:40 | |
| *** |{ame <|{ame!~|{[email protected]> has joined #yosys | 08:23 | |
| |{ame | hello, sorry for the dumb question. I did read the manual, but besides -flatten, I didn't find anything related to multiple submodules. How should I compile a project with submodules? | 08:24 |
|---|---|---|
| gatecat | |{ame: any more details on what you need to do? most of the synthesis flows should deal with them already, usually by flattening | 08:53 |
| |{ame | gatecat: I think I found it. | 09:55 |
| |{ame | I had a file main.v | 09:56 |
| |{ame | which inside instantiates sub sub(....) | 09:56 |
| |{ame | and sub is declared in sub.v | 09:56 |
| |{ame | My Makefile was | 09:56 |
| |{ame | %.json: main.v | 09:56 |
| |{ame | ghdl -a UART_TX.vhd | 09:56 |
| |{ame | ghdl -a UART_RX.vhd | 09:56 |
| |{ame | yosys -p "plugin -i ghdl; ghdl UART_TX; ghdl UART_RX; synth_intel_alm -top spiga -nodsp -nobram; write_json $@" $^ | 09:56 |
| |{ame | and simply changing it to | 09:56 |
| |{ame | %.json: *.v | 09:56 |
| |{ame | it worked | 09:56 |
| |{ame | I do not know if this is the proper way to do it though | 09:56 |
| xiretza[m] | it's not, the make target should depend on the files that are actually required, so main.v sub.v in this case | 10:22 |
| *** tlwoerner <[email protected]> has joined #yosys | 10:42 | |
| *** |{ame <|{ame!~|{[email protected]> has quit IRC (Quit: Client closed) | 11:39 | |
| *** krispaul <[email protected]> has quit IRC (Ping timeout: 268 seconds) | 14:34 | |
| *** krispaul <[email protected]> has joined #yosys | 14:39 | |
| *** Guest66 <[email protected]> has joined #yosys | 14:44 | |
| Guest66 | hello! The following error appeared while using yosys. How to solve it? | 14:46 |
| Guest66 | ERROR: Value conversion failed: `1 'd0' | 14:46 |
| Guest66 | thank you | 14:46 |
| Guest66 | when read_verilog | 14:52 |
| jix | Guest66: can you share more of the input that triggers this error? | 14:55 |
| Guest66 | https://postechackr-my.sharepoint.com/:u:/g/personal/gyu511_postech_ac_kr/Ebuj-uSwauFGrWY9JGkStZoBWJwMBU63kWz56tjyjgtxIw?e=nlCYoy | 14:58 |
| Guest66 | here | 14:58 |
| tpb | Title: Sign in to your account (at postechackr-my.sharepoint.com) | 14:58 |
| Guest66 | and when I ran other verilog file, error has occurred. what is mean?? ERROR: syntax error, unexpected TOK_ID | 15:01 |
| *** so-offishul <[email protected]> has joined #yosys | 15:02 | |
| jix | Guest66: which yosys version are you using? | 15:03 |
| Guest66 | Yosys 0.9 (git sha1 UNKNOWN, clang 10.0.0-4ubuntu1 -fPIC -Os) | 15:03 |
| jix | that is an ancient version, the link you shared loads without errors in a recent version | 15:04 |
| Guest66 | thx how to upgrade? | 15:05 |
| Guest66 | and I have a separate question. Does yosys not consider SDC files? | 15:06 |
| jix | https://github.com/YosysHQ/oss-cad-suite-build#installation is the easiest way to stay up to date | 15:06 |
| Guest66 | really thank you | 15:06 |
| Guest66 | have a nice day | 15:06 |
| *** so-offish <so-offish!~so-offish@2610:148:610:2b11::15> has quit IRC (Ping timeout: 250 seconds) | 15:06 | |
| *** so-offishul <[email protected]> has quit IRC (Quit: Leaving) | 15:18 | |
| *** so-offish <so-offish!~so-offish@2610:148:610:2b11::1b> has joined #yosys | 15:30 | |
| *** Guest66 <[email protected]> has quit IRC (Quit: Client closed) | 15:48 | |
| lofty | Aww, I missed a synth_intel_alm user in the wild | 16:13 |
| *** FabM <FabM!~FabM@armadeus/team/FabM> has quit IRC (Ping timeout: 240 seconds) | 16:26 | |
| *** FabM <FabM!~FabM@2a03:d604:103:600:2e60:8c7c:e8fb:7990> has joined #yosys | 16:26 | |
| *** ZipCPU_ <[email protected]> has joined #yosys | 17:02 | |
| *** ZipCPU <[email protected]> has quit IRC (Ping timeout: 260 seconds) | 17:02 | |
| *** ZipCPU_ is now known as ZipCPU | 17:02 | |
| *** ZipCPU <[email protected]> has quit IRC (Ping timeout: 240 seconds) | 17:22 | |
| *** nak <nak!~nak@yosys/nak> has quit IRC (Ping timeout: 256 seconds) | 17:32 | |
| so-offish | lofty: What's synth_intel_alm? | 17:47 |
| so-offish | lofty: Cyclone V synth (sorry just Googled it) | 17:47 |
| lofty | lofty: written by yours truly | 17:53 |
| lofty | so-offish: ^ | 17:53 |
| so-offish | lofty: Very cool! If you ever want to talk about it I'd be interested. | 18:40 |
| lofty | so-offish: what would you like to know? | 18:59 |
| so-offish | lofty: Can I ask where you started? I mean, was this a techlib for Yosys as a first step, or was there some other first step in the process? I'm trying to think about like "how I would start" if given the same project, and I'm not sure I'd know where to begin | 19:07 |
| lofty | so-offish: the first step is mostly to look at the vendor primitives and what can be implemented in hardware | 19:08 |
| lofty | Then one can implement LUTs and DFFs | 19:10 |
| so-offish | lofty: That would be from a project similar to prjxray, but for Intel parts, correct? | 19:11 |
| lofty | Actually not really | 19:11 |
| lofty | (you're referring to project Mistral, by the way :p) | 19:11 |
| so-offish | lofty: (Thank you; I'm getting up to speed on all the various projects, appreciate the correction) | 19:12 |
| lofty | Anyway | 19:12 |
| lofty | The vendor primitive library gives a few hints, but one can also "just try it and see" | 19:12 |
| lofty | One particularly fun thing to learn is that the flops on a Cyclone V initialise to zero only | 19:13 |
| lofty | Which means you can't have a flop that initialises to zero with an async set | 19:14 |
| so-offish | lofty: Just ran into something similar on the ECP5! I thought I was in crazy town. | 19:14 |
| lofty | so-offish: hmm, on ECP5 it's a boy different | 19:15 |
| lofty | *bit | 19:15 |
| lofty | On ECP5 the initialisation value and the reset value must agree; that is, a flop that initialises to zero must have an async clear | 19:16 |
| so-offish | Let me see, what was I trying to do - I was trying to initialize a FF to a certain value post configuration and found that wasn't supported (or at least I thought) - in this case, it's specific to being unable to async set? | 19:16 |
| so-offish | Ahhh | 19:17 |
| lofty | This is subtly different to the Cyclone V, because the ECP5 can model initialisation to 1 just fine | 19:17 |
| lofty | But for Cyclone V you emulate this using inverters that Yosys silently adds for you | 19:17 |
| lofty | They have the same overall functionality though | 19:18 |
| lofty | Anyway | 19:18 |
| so-offish | The ECP5 can do that? Hm, I thought I had a relatively simple test case where I couldn't detect any difference in the Yosys outputs... | 19:18 |
| *** nak <nak!~nak@yosys/nak> has joined #yosys | 19:18 | |
| so-offish | Maybe I should go re-run my test case before I speak out of turn | 19:18 |
| so-offish | haha | 19:18 |
| lofty | Sure it can do that | 19:19 |
| so-offish | lofty: Ah; interesting that Yosys achieves the same thing with injected inverters. Pretty smart. | 19:19 |
| lofty | Now, I set out to do something that is equal parts brave and dumb | 19:20 |
| lofty | I use ABC9 in synth_intel_alm | 19:20 |
| lofty | Despite it being...quite flaky | 19:20 |
| so-offish | Well...it was an academic showpiece, right? | 19:22 |
| lofty | And to be fair, it's a pretty effective showpiece | 19:23 |
| lofty | But one does run into a lot of ABC9 bugs | 19:23 |
| so-offish | Oh extremely; it wasn't intended as a knock | 19:23 |
| lofty | Now, the relevant information, well, fell off the back of a truck | 19:26 |
| so-offish | The best place to get hard to discover information is from the back of trucks. This is known. | 19:28 |
| lofty | It also helps if your toolchain has a secret debug option to deserialise your databases into plain text and you left that on release | 19:32 |
| lofty | But Altera wouldn't be stupid enough to do that | 19:33 |
| *** krispaul <[email protected]> has quit IRC (Ping timeout: 268 seconds) | 19:38 | |
| *** krispaul <[email protected]> has joined #yosys | 19:47 | |
| *** FabM <FabM!~FabM@armadeus/team/FabM> has quit IRC (Ping timeout: 264 seconds) | 19:51 | |
| Sarayan | you can't really insert an inverter when the ff is on the output of the adder though | 19:57 |
| so-offish | LOLOL | 20:01 |
| *** so-offishul <so-offishul!~so-offish@2610:148:610:2b11::1b> has joined #yosys | 20:10 | |
| *** so-offish <so-offish!~so-offish@2610:148:610:2b11::1b> has quit IRC (Ping timeout: 256 seconds) | 20:12 | |
| *** so-offishul <so-offishul!~so-offish@2610:148:610:2b11::1b> has quit IRC (Quit: Leaving) | 21:12 | |
| *** nonchip <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.) | 22:12 | |
| *** nonchip <[email protected]> has joined #yosys | 22:12 | |
| *** so-offish <so-offish!~so-offish@2610:148:610:2b11::1b> has joined #yosys | 22:57 | |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!