Friday, 2023-05-12

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loftyso-offish: can you paste your Verilog somewhere?03:12
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so-offishlofty: Yeah lemme get that cleared but should be fine brb15:11
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so-offish I think I figured out why what I was doing caused an error17:58
so-offishWhen using TRELLIS_COMB with IS_Z1=1'b1, I had FCI's input tied to 1'b0 - instead I just commented out that input, and I was able to get to routing17:58
so-offishRouting still failed, but that's a new problem17:59
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so-offish No wire found for port F1 on destination cell COMB2.19:56
so-offishBang head on keyboard.19:56
so-offishERROR: Wire X60/Y49/F5_SLICE is used as source and sink in different nets: w0 vs w319:58
so-offishOk, so there must be something I don't know about the way these wires are used between cells (?)19:59
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so-offishWait, for the ECP5, is one comb the IS_Z1=1'b0 and the other is IS_Z1=1'b1, for a given slice?22:32
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