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| singham | Standard cells, shouldn't they differ from foundry to foundry? | 14:13 |
|---|---|---|
| singham | Say there's skywater pdk which creates library for skywater foundry for the specific conditions it has. | 14:14 |
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| singham | If I go for fabricating an IC with AllWinner, for the same, say 130nm, it's cell dimensions, of length and breadth of transistors, etc. would be different right? | 14:15 |
| singham | My question is AND gate at AllWinner foundry and AND gate at Intel Foundry should have different characteristics right, for same dimensions. | 14:21 |
| singham | So my argument is shouldn't libraries should be different for all semiconductor foundries of the world? | 14:22 |
| tnt | They are different ? | 14:23 |
| tnt | Like each foundry provides their standard cell libs. | 14:23 |
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| singham | Yes | 14:23 |
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| tnt | (often several of them actually ... depending if you want low power / high speed / ... ) | 14:24 |
| singham | So say, I design an AND gate for skywater foundry, say it has 20nm width and 40nm high, with the right proportions for n doped, oxide, p doped all that | 14:25 |
| singham | If I move that as it is to Intel foundry, won't my design falter? | 14:25 |
| tnt | Depends on each process ... some are actually "kinda" compatible. Like for instance ECP5 was moved from one process to another. Athough done by different foundries those were compatible. | 14:26 |
| tnt | (they did bunch of re-validation etc ... you can read about it in some pdf that I can't recall exactly how to find, but it's out there) | 14:27 |
| singham | tnt: What do you do? Your work? | 14:28 |
| tnt | I'm a FPGA designer. I don't do asic for work, this is just "basic" knowledge from dabbing into sky130 / gf180. | 14:29 |
| singham | Wow! Cool, man! | 14:29 |
| singham | I heard a nice joke by Clive on FPGAs | 14:30 |
| singham | FPGA designers have so much complexity in routing and connections, that they throw in CLBs as a bonus! | 14:31 |
| tnt | Ok, to be clear, what I meant is I do designs running on FPGA, I don't design the FPGA themselves. ( i.e. see the next sentence where I say "I don't do asic for work" ). | 14:32 |
| singham | Aah ok :) | 14:34 |
| singham | Nice. | 14:34 |
| singham | Last 2 days I learnt quite a lot on physical design of FPGAs | 14:34 |
| singham | Gowin semiconductor boards are quite powerful! | 14:35 |
| singham | I saw lately, 20k LUTs. | 14:35 |
| singham | I'm waiting for their SRAM ones to be supported by yosys nextpnr | 14:35 |
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| so-offish | Whats up everyoen | 17:32 |
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