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so-offish | Is TRELLIS_SLICE no longer supported in nextpnr? | 18:14 |
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tnt | No, AFAIK it got split. | 18:16 |
so-offish | Yeah it looks like it got split but it's listed as a supported primitive (also Yosys will merrily still spit out TRELLIS_SLICE as a valid techlib cell) | 18:17 |
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datenwolf | Hi, everone. If I intended to hack on the nextpnr GUI, which would be the most sensible tag/commit to start from right now? | 18:19 |
tnt | so-offish: When does yosys emit it ? | 18:21 |
tnt | so-offish: you mean if you instanciate it ? Well yeah, I think it'll be happy to emit whatever. It's still in the sim models to allow sim of old stuff but it shouldn't emit any by itself. | 18:25 |
so-offish | tnt: You're right, it's instantiated. I see what you mean: It won't take some set of combinatorial and clock logic and use a TRELLIS_SLICE for this. | 18:28 |
lofty | so-offish: split slice has a lot of technical advantages, which is why it was done. the downside is that manual instantiation of TRELLIS_SLICE broke | 18:58 |
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lofty | datenwolf: I don't think the GUI stuff is touched much, so it shouldn't matter, but I would still follow git master in this case | 19:45 |
datenwolf | thanks. Mostly I want to go after Qt complaining about an unhandled exception reaching its signals/slots system. | 19:47 |
datenwolf | and by that I mean: Figure out what's throwing that exception, figure out why it's called in a UI context, address that, and then fix whatever is causing that exception in the first place | 19:50 |
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so-offish | lofty: There is no TRELLIS_COMB in the cells_sim.v for Yosys; does that always map 1:1 to just LUT4? | 23:51 |
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