Sunday, 2023-03-05

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SarayanzipCPU: the cycloneV ddr handling is a combination of a HMC (hard memory controller), some delay lines, dynamic termination control, pll and who knows what else.  Plus code on a cpu (either hps or nios2) to calibrate the stuff.  I suspect the general principles are fpga-independant, and the code half-independant too09:48
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ZipCPUThe problem is that the "hard memory controller" is not fpga-independent.  Every FPGA has their own implementation of it.  That makes it hard to port something from one device to another.13:34
ZipCPUWorse, many FPGAs don't document the hard part of their memory controller.13:53
Sarayansure, but otoh half the calibration code is probably fpga-independant14:26
Sarayanand what is needed/the concepts are similarly transverse14:27
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