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| marex | Hi, looking at https://github.com/YosysHQ/yosys/tree/master/techlibs/intel , do I understand it right that yosys is now able to assemble a bitstream for altera pre-alm FPGAs ? :O | 00:29 |
|---|---|---|
| marex | entirely without quartus ? | 00:29 |
| whitequark | no | 01:01 |
| whitequark | it only did synthesis and it kind of doesn't anymore, that techlib is very old and I think untested | 01:01 |
| marex | whitequark: oh, so, where do I find out which FPGAs are actually fully supported, so I know what to buy and what to avoid ? | 01:02 |
| marex | the ice40 is obvious, maybe the gatemate is also OK ? but what else ? | 01:02 |
| mwk | it's.... actually tested, with a big red QA FAIL stamped on it | 01:03 |
| whitequark | ice40, ecp5 | 01:03 |
| marex | ah right, ecp5 too | 01:03 |
| whitequark | gowin, I think? | 01:03 |
| marex | I recall seeing something for that too | 01:04 |
| marex | I got confused by the altera stuff, since I think rqou worked on it https://github.com/ArcaneNibble/project-chibi here | 01:04 |
| whitequark | nexus if you can find those | 01:04 |
| marex | and it seems the evil/ subdir would indicate that err ... well, it might be possible to read out the FPGA topologies from quartus data files, just by parsing those | 01:04 |
| marex | I'm not quite sure how that is license-wise, it might be dubious | 01:05 |
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| marex | whitequark: can I somehow grep the sources to find out what is supported now ? | 01:07 |
| whitequark | you can look at nextpnr's README | 01:09 |
| whitequark | since nextpnr is what actually makes the bitstream | 01:09 |
| marex | ahhh, that is what I was looking for, thanks ! | 01:09 |
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| jn | Hi, i have a question about prjtrellis and MachXO2: what's a "row span"? (as seen in https://github.com/YosysHQ/prjtrellis/blob/master/tools/gen_globals.py#L23) | 17:52 |
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