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| whitequark | i just set logging up | 00:33 |
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| cr1901 | If I have a design with a clock enable, is there a way to get nextpnr to tell me "minimum period of the clock enable signal to propogate throughout the design"? | 20:08 |
| cr1901 | Idea being "I want to embed the design in a clock domain faster than "Fmax when clock enable isn't used"" | 20:08 |
| tnt | Nope | 20:16 |
| tnt | But you can probaby just deduce that yourself from the fmax of your design. | 20:17 |
| cr1901 | Well, "Fmax of the entire design when the sub-design has its clock enable signal used" divided by "number of cycles clock enable inactive + 1" is certainly an upper bound to "Fmax of the subdesign when ce is used" | 20:22 |
| tnt | But even if you knew that number, there is no support for multi-cycle constrainst in current nextpnr. | 20:25 |
| tnt | I know there was some discussions I've seen on github, but ATM AFAIK nothing in mainline. | 20:26 |
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| cr1901 | What's a multi-cycle constraint, specifically? Is it "the term for the scenario I just described", or something more specific? | 20:45 |
| tnt | It's when you tell the tools that some paths should be constrained to a multiple of the period. This is what is typically used to describe that you have a CE and it's only active once every N cycles. | 20:50 |
| tnt | https://nl.mathworks.com/help/hdlcoder/ug/enable-based-multicycle-constraints.html | 20:53 |
| tpb | Title: Meet Timing Requirements Using Enable-Based Multicycle Path Constraints - MATLAB & Simulink - MathWorks Benelux (at nl.mathworks.com) | 20:53 |
| cr1901 | tyvm | 21:03 |
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