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Sarayan | Hi, yosys oss does not have vhdl? | 14:12 |
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tnt | Not natively. | 14:27 |
tnt | There is a GHDL plugin that allows VHDL input. | 14:28 |
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ikskuh | tnt: does that mean i could make projects that mix VHDL and Verilog? | 16:15 |
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xiretza[m] | yes | 18:10 |
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ikskuh | that is pretty cool | 19:17 |
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whitequark | you could even mix VHDL, Verilog and Amaranth, with any of them anywhere in the hierarchy | 20:57 |
whitequark | (any HDL that supports the Yosys RPC protocol, really) | 20:57 |
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ikskuh | uuh, sounds nice | 21:14 |
ikskuh | is there a HDL somewhere between Verilog and VHDL? | 21:14 |
ikskuh | i honestly like the syntax of verilog, but it's way too lax | 21:14 |
corecode | regarding types? | 21:16 |
corecode | i wanted to get into formal verification, but i don't know how to start | 21:16 |
ikskuh | yeah, at least some type checking would be nice | 21:17 |
ikskuh | and a modern module management | 21:17 |
corecode | systemverilog? | 21:17 |
bjorkintosh | corecode, from the beginning. | 21:17 |
corecode | not supported in the free version tho | 21:17 |
bjorkintosh | that's usually a good place. | 21:17 |
corecode | bjorkintosh: yet here we are | 21:17 |
bjorkintosh | Logic. | 21:18 |
ikskuh | i am confuse now | 21:18 |
corecode | bjorkintosh: my brain is just not trained to think in explicit (temporal) invariants | 21:18 |
corecode | ikskuh: about? | 21:19 |
ikskuh | the last 6 lines of text before that message | 21:19 |
bjorkintosh | corecode, maybe chatgpt will do all the hard verification work and we'll just sit back and watch. | 21:23 |
ikskuh | lol | 21:23 |
bjorkintosh | corecode, seriously. try it and see. | 21:29 |
corecode | bjorkintosh: you mean try chatgpt? | 21:56 |
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bjorkintosh | sure. | 22:41 |
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corecode | i don't even know how to start | 22:54 |
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bjorkintosh | where have I heard that before? | 23:16 |
bjorkintosh | <corecode> i wanted to get into formal verification, but i don't know how to start | 23:16 |
corecode | yes, it's the same issue | 23:24 |
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