Saturday, 2023-01-14

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SarayanHi, yosys oss does not have vhdl?14:12
tntNot natively.14:27
tntThere is a GHDL plugin that allows VHDL input.14:28
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ikskuhtnt: does that mean i could make projects that mix VHDL and Verilog?16:15
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xiretza[m]yes18:10
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ikskuhthat is pretty cool19:17
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whitequarkyou could even mix VHDL, Verilog and Amaranth, with any of them anywhere in the hierarchy20:57
whitequark(any HDL that supports the Yosys RPC protocol, really)20:57
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ikskuhuuh, sounds nice21:14
ikskuhis there a HDL somewhere between Verilog and VHDL?21:14
ikskuhi honestly like the syntax of verilog, but it's way too lax 21:14
corecoderegarding types?21:16
corecodei wanted to get into formal verification, but i don't know how to start21:16
ikskuhyeah, at least some type checking would be nice21:17
ikskuhand a modern module management21:17
corecodesystemverilog?21:17
bjorkintoshcorecode, from the beginning.21:17
corecodenot supported in the free version tho21:17
bjorkintoshthat's usually a good place.21:17
corecodebjorkintosh: yet here we are21:17
bjorkintoshLogic.21:18
ikskuhi am confuse now21:18
corecodebjorkintosh: my brain is just not trained to think in explicit (temporal) invariants21:18
corecodeikskuh: about?21:19
ikskuhthe last 6 lines of text before that message21:19
bjorkintoshcorecode, maybe chatgpt will do all the hard verification work and we'll just sit back and watch.21:23
ikskuhlol21:23
bjorkintoshcorecode, seriously. try it and see.21:29
corecodebjorkintosh: you mean try chatgpt?21:56
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bjorkintoshsure.22:41
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corecodei don't even know how to start22:54
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bjorkintoshwhere have I heard that before?23:16
bjorkintosh<corecode> i wanted to get into formal verification, but i don't know how to start 23:16
corecodeyes, it's the same issue23:24
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