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| ere | is there separate chat for gowin? | 09:30 |
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| Sarayan | ERROR: Multiple edge sensitive events found for this signal! | 11:50 |
| Sarayan | that means multiple writes? | 11:50 |
| Sarayan | it's setting is in a always @(posedge clk32, negedge porb, negedge resb) begin | 11:51 |
| Sarayan | og.kervella.org/gstmcu.v signal ixdma, comes from AtariST_Mister | 11:52 |
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| jix | Sarayan: AFAICT it's just that both porb as well as resb cause an async reset of ixdma, but yosys' FF cells can only have one ALOAD input | 12:29 |
| jix | (or an async reset instead of async load, but still same limitation) | 12:31 |
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| jix | since the actual modelled behavior is just a level sensitive async reset when either of them is low, it's possible to use a single FF and connect the and of both of them to the async reset input | 12:35 |
| Sarayan | thanks, gonna try that | 12:39 |
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| jix | wait, maybe it's not this | 12:40 |
| Sarayan | yeah, doesn't change a thing | 12:42 |
| Sarayan | fwiw I'm trying to build a sim using og.kervella.org/yosys.sh | 12:47 |
| Sarayan | that coe overuses edges | 12:48 |
| Sarayan | code | 12:48 |
| jix | so with https://gist.githubusercontent.com/jix/8e496022a582163c29027891526f943d/raw/bcdadb003ee5d599dccf6678b6826b4e79fe1b16/gstmcu.diff I don't get that error | 12:53 |
| jix | (the "wait, ..." was just me not noticing a typo I had made) | 12:54 |
| jix | I haven't really used cxxrtl myself, but when the design does lot of async stuff it might not work as is due to stuff like this https://github.com/YosysHQ/yosys/issues/3549 | 12:56 |
| jix | the good news is that (depending on how the design uses async stuff) you might still be able to simulate it by using async2sync or clk2fflogic to convert it to a sync design before running it through cxxrtl | 12:57 |
| jix | Sarayan: https://gist.githubusercontent.com/jix/56611ea81664ea7df15e2cea5424e745/raw/86de9be17749cf46342349d7bc94182f97447bd3/gstmcu.2.diff also works | 13:02 |
| jix | so the frontend does have the logic to combine multiple level sensitive resets (I also did vaguely remember seeing this), it just doesn't recognize the particular pattern used | 13:03 |
| Sarayan | oh cute | 13:05 |
| Sarayan | much thanks | 13:05 |
| Sarayan | yep, once I've added the missing modules cxxrtl generates the .cc, beautiful | 13:09 |
| jix | the two ways that work also do match IEEE 1364.1 "Standard for Verilog Register Transfer Level Synthesis" while the original doesn't | 13:10 |
| jix | not that yosys is limiting itself to that, lots of real world RTL doesn't strictly follow that and other tools do support more too, but following that probably still is a good way to make sure synthesis works and matches across tools | 13:11 |
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| Sarayan | that all confirms my clear preference for amaranth | 13:12 |
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| lofty | ere: #yosys-apicula | 20:08 |
| ere | lofty: thanks | 20:32 |
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