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| Guest8 | Hi , | 11:14 |
|---|---|---|
| Guest8 | How to set dont use library cells for some library cells based on pattern : like set_dont_use /XOR3 | 11:14 |
| Guest8 | Using version : Yosys 0.23+45 (git sha1 a64ed82, clang 10.0.0-4ubuntu1 -fPIC -Os) | 11:14 |
| Guest8 | Thanks | 11:14 |
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| bjonnh | Hi, I'm trying to compile this verilog module: https://gist.github.com/bjonnh/16f64872e62fb86ef429c98abce330fc | 22:13 |
| bjonnh | and I get top.v:37: ERROR: syntax error, unexpected '(', expecting OP_CAST | 22:14 |
| bjonnh | This seems to be related to those two entries with signed( on them. If I comment that code, I get an error on line 51 about ERROR: syntax error, unexpected TOK_CONSTVAL | 22:15 |
| bjonnh | To me this all look like normal verilog I can't really get what's wrong with it. | 22:15 |
| tnt | b'00 should be 2'b00 | 22:22 |
| tnt | signed should be $signed AFAIR | 22:22 |
| bjonnh | Thanks, I found that here: https://github.com/AndrewJones-PSU/I2S2Test I suppose they use some kind of vendor specific verilog? | 22:23 |
| tnt | or systemverilog | 22:23 |
| bjonnh | oh so systemverilog IS different from verilog | 22:24 |
| bjonnh | I wasn't sure as I gave the ECP PLL example (that is in systemverilog) directly to yosys and it was happy with it | 22:24 |
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| bjonnh | tnt: Thanks, that works now. | 22:28 |
| bjonnh | Well... still no sound out, but at least that compiles | 22:37 |
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